From 9662f102e5c2ebdf58cb1debeb7864179696f8b6 Mon Sep 17 00:00:00 2001
From: Jakob Stoklund Olesen <jolesen@mozilla.com>
Date: Wed, 5 Jul 2017 15:12:35 -0700
Subject: [PATCH] Intel 32-bit encodings for copy.i32.

---
 cranelift/filetests/isa/intel/binary32.cton |  5 +++++
 lib/cretonne/meta/isa/intel/encodings.py    |  2 ++
 lib/cretonne/meta/isa/intel/recipes.py      |  8 ++++++--
 lib/cretonne/src/isa/intel/binemit.rs       | 10 ++++++++++
 4 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/cranelift/filetests/isa/intel/binary32.cton b/cranelift/filetests/isa/intel/binary32.cton
index 2e42d01fcc..14f050c2e7 100644
--- a/cranelift/filetests/isa/intel/binary32.cton
+++ b/cranelift/filetests/isa/intel/binary32.cton
@@ -56,6 +56,11 @@ ebb0:
     ; asm: sarl %cl, %ecx
     [-,%rcx]             v25 = sshr v1, v1       ; bin: d3 f9
 
+    ; asm: movl %esi, %ecx
+    [-,%rcx]             v26 = copy v2           ; bin: 89 f1
+    ; asm: movl %ecx, %esi
+    [-,%rsi]             v27 = copy v1           ; bin: 89 ce
+
     ; Integer Register - Immediate 8-bit operations.
     ; The 8-bit immediate is sign-extended.
 
diff --git a/lib/cretonne/meta/isa/intel/encodings.py b/lib/cretonne/meta/isa/intel/encodings.py
index c05308177a..0b59b32da3 100644
--- a/lib/cretonne/meta/isa/intel/encodings.py
+++ b/lib/cretonne/meta/isa/intel/encodings.py
@@ -13,6 +13,8 @@ I32.enc(base.band.i32, *r.rr(0x21))
 I32.enc(base.bor.i32,  *r.rr(0x09))
 I32.enc(base.bxor.i32, *r.rr(0x31))
 
+I32.enc(base.copy.i32, *r.ur(0x89))
+
 # Immediate instructions with sign-extended 8-bit and 32-bit immediate.
 for inst,                   rrr in [
         (base.iadd_imm.i32, 0),
diff --git a/lib/cretonne/meta/isa/intel/recipes.py b/lib/cretonne/meta/isa/intel/recipes.py
index 4e41c9b990..3700ff60b5 100644
--- a/lib/cretonne/meta/isa/intel/recipes.py
+++ b/lib/cretonne/meta/isa/intel/recipes.py
@@ -4,8 +4,8 @@ Intel Encoding recipes.
 from __future__ import absolute_import
 from cdsl.isa import EncRecipe
 from cdsl.predicates import IsSignedInt, IsEqual
-from base.formats import UnaryImm, Binary, BinaryImm, Store, Load
-from base.formats import MultiAry, Call, IndirectCall
+from base.formats import Unary, UnaryImm, Binary, BinaryImm, MultiAry
+from base.formats import Call, IndirectCall, Store, Load
 from .registers import GPR, ABCD
 
 try:
@@ -143,6 +143,10 @@ class TailRecipe:
 # XX /r
 rr = TailRecipe('rr', Binary, size=1, ins=(GPR, GPR), outs=0)
 
+# XX /r, but for a unary operator with separate input/output register, like
+# copies.
+ur = TailRecipe('ur', Unary, size=1, ins=GPR, outs=GPR)
+
 # XX /n with one arg in %rcx, for shifts.
 rc = TailRecipe('rc', Binary, size=1, ins=(GPR, GPR.rcx), outs=0)
 
diff --git a/lib/cretonne/src/isa/intel/binemit.rs b/lib/cretonne/src/isa/intel/binemit.rs
index 001a41e009..10bd6288a7 100644
--- a/lib/cretonne/src/isa/intel/binemit.rs
+++ b/lib/cretonne/src/isa/intel/binemit.rs
@@ -111,6 +111,16 @@ fn recipe_op1rr<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut C
     }
 }
 
+fn recipe_op1ur<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
+    if let InstructionData::Unary { arg, .. } = func.dfg[inst] {
+        put_op1(func.encodings[inst].bits(), sink);
+        let res = func.locations[func.dfg.first_result(inst)].unwrap_reg();
+        modrm_rr(res, func.locations[arg].unwrap_reg(), sink);
+    } else {
+        panic!("Expected Unary format: {:?}", func.dfg[inst]);
+    }
+}
+
 fn recipe_op1rc<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
     if let InstructionData::Binary { args, .. } = func.dfg[inst] {
         let bits = func.encodings[inst].bits();