Encodings for load/store instructions.
We don't support the full set of Intel addressing modes yet. So far we have: - Register indirect, no displacement. - Register indirect, 8-bit signed displacement. - Register indirect, 32-bit signed displacement. The SIB addressing modes will need new Cretonne instruction formats to represent.
This commit is contained in:
Jakob Stoklund Olesen
@@ -3,9 +3,9 @@ Intel Encoding recipes.
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"""
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from __future__ import absolute_import
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from cdsl.isa import EncRecipe
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from cdsl.predicates import IsSignedInt
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from base.formats import Binary, BinaryImm
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from .registers import GPR
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from cdsl.predicates import IsSignedInt, IsEqual
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from base.formats import Binary, BinaryImm, Store, Load
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from .registers import GPR, ABCD
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# Opcode representation.
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#
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@@ -15,21 +15,21 @@ from .registers import GPR
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# name prefix:
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#
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# <op> Op1* OP(op)
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# 0F <op> Op2* OP(op)
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# 0F <op> Op2* OP0F(op)
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# 0F 38 <op> Op3* OP38(op)
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# 0F 3A <op> Op3* OP3A(op)
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# 66 <op> Mp1* MP66(op)
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# 66 0F <op> Mp2* MP66(op)
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# 66 0F 38 <op> Mp3* MP6638(op)
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# 66 0F 3A <op> Mp3* MP663A(op)
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# 66 0F <op> Mp2* MP660F(op)
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# 66 0F 38 <op> Mp3* MP660F38(op)
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# 66 0F 3A <op> Mp3* MP660F3A(op)
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# F2 <op> Mp1* MPF2(op)
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# F2 0F <op> Mp2* MPF2(op)
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# F2 0F 38 <op> Mp3* MPF238(op)
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# F2 0F 3A <op> Mp3* MPF23A(op)
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# F2 0F <op> Mp2* MPF20F(op)
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# F2 0F 38 <op> Mp3* MPF20F38(op)
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# F2 0F 3A <op> Mp3* MPF20F3A(op)
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# F3 <op> Mp1* MPF3(op)
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# F3 0F <op> Mp2* MPF3(op)
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# F3 0F 38 <op> Mp3* MPF338(op)
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# F3 0F 3A <op> Mp3* MPF33A(op)
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# F3 0F <op> Mp2* MP0FF3(op)
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# F3 0F 38 <op> Mp3* MPF30F38(op)
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# F3 0F 3A <op> Mp3* MPF30F3A(op)
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#
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# VEX/XOP and EVEX prefixes are not yet supported.
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#
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@@ -63,6 +63,16 @@ def OP(op, pp=0, mm=0, rrr=0, w=0):
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return op | (pp << 8) | (mm << 10) | (rrr << 12) | (w << 15)
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def OP0F(op, rrr=0, w=0):
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# type: (int, int, int) -> int
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return OP(op, pp=0, mm=1, rrr=rrr, w=w)
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def MP66(op, rrr=0, w=0):
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# type: (int, int, int) -> int
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return OP(op, pp=1, mm=0, rrr=rrr, w=w)
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# XX /r
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Op1rr = EncRecipe('Op1rr', Binary, size=2, ins=(GPR, GPR), outs=0)
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@@ -78,3 +88,78 @@ Op1rib = EncRecipe(
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Op1rid = EncRecipe(
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'Op1rid', BinaryImm, size=6, ins=GPR, outs=0,
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instp=IsSignedInt(BinaryImm.imm, 32))
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#
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# Store recipes.
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#
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# XX /r register-indirect store with no offset.
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Op1st = EncRecipe(
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'Op1st', Store, size=2, ins=(GPR, GPR), outs=(),
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instp=IsEqual(Store.offset, 0))
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# XX /r register-indirect store with no offset.
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# Only ABCD allowed for stored value. This is for byte stores.
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Op1st_abcd = EncRecipe(
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'Op1st_abcd', Store, size=2, ins=(ABCD, GPR), outs=(),
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instp=IsEqual(Store.offset, 0))
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# XX /r register-indirect store with 8-bit offset.
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Op1stDisp8 = EncRecipe(
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'Op1stDisp8', Store, size=3, ins=(GPR, GPR), outs=(),
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instp=IsSignedInt(Store.offset, 8))
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Op1stDisp8_abcd = EncRecipe(
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'Op1stDisp8_abcd', Store, size=3, ins=(ABCD, GPR), outs=(),
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instp=IsSignedInt(Store.offset, 8))
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# XX /r register-indirect store with 32-bit offset.
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Op1stDisp32 = EncRecipe('Op1stDisp32', Store, size=6, ins=(GPR, GPR), outs=())
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Op1stDisp32_abcd = EncRecipe(
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'Op1stDisp32_abcd', Store, size=6, ins=(ABCD, GPR), outs=())
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# PP WW /r register-indirect store with no offset.
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Mp1st = EncRecipe(
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'Mp1st', Store, size=3, ins=(GPR, GPR), outs=(),
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instp=IsEqual(Store.offset, 0))
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# PP XX /r register-indirect store with 8-bit offset.
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Mp1stDisp8 = EncRecipe(
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'Mp1stDisp8', Store, size=4, ins=(GPR, GPR), outs=(),
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instp=IsSignedInt(Store.offset, 8))
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# PP XX /r register-indirect store with 32-bit offset.
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Mp1stDisp32 = EncRecipe('Mp1stDisp32', Store, size=7, ins=(GPR, GPR), outs=())
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#
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# Load recipes
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#
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# XX /r load with no offset.
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Op1ld = EncRecipe(
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'Op1ld', Load, size=2, ins=(GPR), outs=(GPR),
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instp=IsEqual(Load.offset, 0))
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# XX /r load with 8-bit offset.
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Op1ldDisp8 = EncRecipe(
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'Op1ldDisp8', Load, size=3, ins=(GPR), outs=(GPR),
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instp=IsSignedInt(Load.offset, 8))
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# XX /r load with 32-bit offset.
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Op1ldDisp32 = EncRecipe(
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'Op1ldDisp32', Load, size=6, ins=(GPR), outs=(GPR),
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instp=IsSignedInt(Load.offset, 32))
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# 0F XX /r load with no offset.
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Op2ld = EncRecipe(
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'Op2ld', Load, size=3, ins=(GPR), outs=(GPR),
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instp=IsEqual(Load.offset, 0))
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# XX /r load with 8-bit offset.
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Op2ldDisp8 = EncRecipe(
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'Op2ldDisp8', Load, size=4, ins=(GPR), outs=(GPR),
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instp=IsSignedInt(Load.offset, 8))
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# XX /r load with 32-bit offset.
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Op2ldDisp32 = EncRecipe(
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'Op2ldDisp32', Load, size=7, ins=(GPR), outs=(GPR),
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instp=IsSignedInt(Load.offset, 32))
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