Merge raw_bitcast and bitcast (#5175)

- Allow bitcast for vectors with differing lane widths
- Remove raw_bitcast IR instruction
- Change all users of raw_bitcast to bitcast
- Implement support for no-op bitcast cases across backends

This implements the second step of the plan outlined here:
https://github.com/bytecodealliance/wasmtime/issues/4566#issuecomment-1234819394

cranelift/filetests/filetests/isa/x64/move-elision.clif

@@ -7,9 +7,9 @@ block0(v0: i32x4):
     ;; In the x64 backend, all of these pseudo-instructions are lowered to moves between registers (e.g. MOVAPD, MOVDQA,
     ;; etc.). Because these have been marked as moves, no instructions are emitted by this function besides the prologue
     ;; and epilogue.
-    v1 = raw_bitcast.f32x4 v0
-    v2 = raw_bitcast.f64x2 v1
-    v3 = raw_bitcast.i8x16 v2
+    v1 = bitcast.f32x4 v0
+    v2 = bitcast.f64x2 v1
+    v3 = bitcast.i8x16 v2
     return v3
 }
 

cranelift/filetests/filetests/isa/x64/simd-issue-3951.clif

@@ -12,7 +12,7 @@ function %check_issue_3951(i64 vmctx) -> i8x16 fast {
     v4 = global_value.i64 gv0
     v5 = load.i8x16 notrap aligned v4+8
     v6 = icmp ugt v3, v5
-    v7 = raw_bitcast.i8x16 v6
+    v7 = bitcast.i8x16 v6
     jump block1(v7)
   block1(v1: i8x16):
     return v1