Merge raw_bitcast and bitcast (#5175)
- Allow bitcast for vectors with differing lane widths - Remove raw_bitcast IR instruction - Change all users of raw_bitcast to bitcast - Implement support for no-op bitcast cases across backends This implements the second step of the plan outlined here: https://github.com/bytecodealliance/wasmtime/issues/4566#issuecomment-1234819394
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@@ -1760,16 +1760,25 @@
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(rule (lower (has_type $I32 (bitcast x @ (value_type $F32))))
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(vec_extract_lane $F32X4 x 0 (zero_reg)))
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;; Bitcast between types residing in GPRs is a no-op.
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(rule 1 (lower (has_type (gpr32_ty _)
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(bitcast x @ (value_type (gpr32_ty _))))) x)
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(rule 2 (lower (has_type (gpr64_ty _)
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(bitcast x @ (value_type (gpr64_ty _))))) x)
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;;;; Rules for `raw_bitcast` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Bitcast between types residing in FPRs is a no-op.
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(rule 3 (lower (has_type (ty_scalar_float _)
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(bitcast x @ (value_type (ty_scalar_float _))))) x)
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;; FIXME: There are two flavors of raw_bitcast, which are currently not
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;; Bitcast between types residing in VRs is a no-op.
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;; FIXME: There are two flavors of vector bitcast, which are currently not
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;; distinguished in CLIF IR. Those generated by Wasmtime assume little-endian
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;; lane order, and those generated elsewhere assume big-endian lane order.
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;; Raw bitcast is a no-op if current lane order matches that assumed lane order.
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;; Bitcast is a no-op if current lane order matches that assumed lane order.
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;; However, due to our choice of lane order depending on the current function
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;; ABI, every bitcast we currently see here is indeed a no-op.
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(rule (lower (raw_bitcast x)) x)
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(rule 4 (lower (has_type (vr128_ty _)
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(bitcast x @ (value_type (vr128_ty _))))) x)
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;;;; Rules for `insertlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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@@ -141,7 +141,6 @@ impl LowerBackend for S390xBackend {
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| Opcode::ScalarToVector
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| Opcode::VhighBits
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| Opcode::Bitcast
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| Opcode::RawBitcast
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| Opcode::Load
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| Opcode::Uload8
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| Opcode::Sload8
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