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AArch64: Introduce an enum to specify vector instruction operand sizes

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Copyright (c) 2020, Arm Limited.
This commit is contained in:
Anton Kirilov
2020-06-19 01:00:47 +01:00
parent bc1e960b9e
commit 95b0b05af2
7 changed files with 374 additions and 388 deletions
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250
cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
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@@ -1841,7 +1841,7 @@ fn test_aarch64_binemit() {
rd: writable_xreg(3),
rn: vreg(27),
idx: 14,
ty: I8,
size: VectorSize::Size8x16,
},
"633F1D0E",
"umov w3, v27.b[14]",
@@ -1851,7 +1851,7 @@ fn test_aarch64_binemit() {
rd: writable_xreg(24),
rn: vreg(5),
idx: 3,
ty: I16,
size: VectorSize::Size16x8,
},
"B83C0E0E",
"umov w24, v5.h[3]",
@@ -1861,7 +1861,7 @@ fn test_aarch64_binemit() {
rd: writable_xreg(12),
rn: vreg(17),
idx: 1,
ty: I32,
size: VectorSize::Size32x4,
},
"2C3E0C0E",
"mov w12, v17.s[1]",
@@ -1871,7 +1871,7 @@ fn test_aarch64_binemit() {
rd: writable_xreg(21),
rn: vreg(20),
idx: 0,
ty: I64,
size: VectorSize::Size64x2,
},
"953E084E",
"mov x21, v20.d[0]",
@@ -1900,7 +1900,7 @@ fn test_aarch64_binemit() {
Inst::VecDup {
rd: writable_vreg(25),
rn: xreg(7),
ty: I8,
size: VectorSize::Size8x16,
},
"F90C014E",
"dup v25.16b, w7",
@@ -1909,7 +1909,7 @@ fn test_aarch64_binemit() {
Inst::VecDup {
rd: writable_vreg(2),
rn: xreg(23),
ty: I16,
size: VectorSize::Size16x8,
},
"E20E024E",
"dup v2.8h, w23",
@@ -1918,7 +1918,7 @@ fn test_aarch64_binemit() {
Inst::VecDup {
rd: writable_vreg(0),
rn: xreg(28),
ty: I32,
size: VectorSize::Size32x4,
},
"800F044E",
"dup v0.4s, w28",
@@ -1927,7 +1927,7 @@ fn test_aarch64_binemit() {
Inst::VecDup {
rd: writable_vreg(31),
rn: xreg(5),
ty: I64,
size: VectorSize::Size64x2,
},
"BF0C084E",
"dup v31.2d, x5",
@@ -1936,7 +1936,7 @@ fn test_aarch64_binemit() {
Inst::VecDupFromFpu {
rd: writable_vreg(14),
rn: vreg(19),
ty: F32,
size: VectorSize::Size32x4,
},
"6E06044E",
"dup v14.4s, v19.s[0]",
@@ -1945,7 +1945,7 @@ fn test_aarch64_binemit() {
Inst::VecDupFromFpu {
rd: writable_vreg(18),
rn: vreg(10),
ty: F64,
size: VectorSize::Size64x2,
},
"5205084E",
"dup v18.2d, v10.d[0]",
@@ -2004,50 +2004,6 @@ fn test_aarch64_binemit() {
"5CA4202F",
"uxtl v28.2d, v2.2s",
));
insns.push((
Inst::VecRRR {
rd: writable_vreg(21),
rn: vreg(22),
rm: vreg(23),
alu_op: VecALUOp::UQAddScalar,
ty: I64,
},
"D50EF77E",
"uqadd d21, d22, d23",
));
insns.push((
Inst::VecRRR {
rd: writable_vreg(21),
rn: vreg(22),
rm: vreg(23),
alu_op: VecALUOp::SQAddScalar,
ty: I64,
},
"D50EF75E",
"sqadd d21, d22, d23",
));
insns.push((
Inst::VecRRR {
rd: writable_vreg(21),
rn: vreg(22),
rm: vreg(23),
alu_op: VecALUOp::UQSubScalar,
ty: I64,
},
"D52EF77E",
"uqsub d21, d22, d23",
));
insns.push((
Inst::VecRRR {
rd: writable_vreg(21),
rn: vreg(22),
rm: vreg(23),
alu_op: VecALUOp::SQSubScalar,
ty: I64,
},
"D52EF75E",
"sqsub d21, d22, d23",
));
insns.push((
Inst::VecRRR {
@@ -2055,7 +2011,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(1),
rn: vreg(2),
rm: vreg(8),
ty: I8X16,
size: VectorSize::Size8x16,
},
"410C284E",
"sqadd v1.16b, v2.16b, v8.16b",
@@ -2067,7 +2023,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(1),
rn: vreg(12),
rm: vreg(28),
ty: I16X8,
size: VectorSize::Size16x8,
},
"810D7C4E",
"sqadd v1.8h, v12.8h, v28.8h",
@@ -2079,7 +2035,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(12),
rn: vreg(2),
rm: vreg(6),
ty: I32X4,
size: VectorSize::Size32x4,
},
"4C0CA64E",
"sqadd v12.4s, v2.4s, v6.4s",
@@ -2091,7 +2047,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(20),
rn: vreg(7),
rm: vreg(13),
ty: I64X2,
size: VectorSize::Size64x2,
},
"F40CED4E",
"sqadd v20.2d, v7.2d, v13.2d",
@@ -2103,7 +2059,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(1),
rn: vreg(2),
rm: vreg(8),
ty: I8X16,
size: VectorSize::Size8x16,
},
"412C284E",
"sqsub v1.16b, v2.16b, v8.16b",
@@ -2115,7 +2071,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(1),
rn: vreg(12),
rm: vreg(28),
ty: I16X8,
size: VectorSize::Size16x8,
},
"812D7C4E",
"sqsub v1.8h, v12.8h, v28.8h",
@@ -2127,7 +2083,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(12),
rn: vreg(2),
rm: vreg(6),
ty: I32X4,
size: VectorSize::Size32x4,
},
"4C2CA64E",
"sqsub v12.4s, v2.4s, v6.4s",
@@ -2139,7 +2095,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(20),
rn: vreg(7),
rm: vreg(13),
ty: I64X2,
size: VectorSize::Size64x2,
},
"F42CED4E",
"sqsub v20.2d, v7.2d, v13.2d",
@@ -2151,7 +2107,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(1),
rn: vreg(2),
rm: vreg(8),
ty: I8X16,
size: VectorSize::Size8x16,
},
"410C286E",
"uqadd v1.16b, v2.16b, v8.16b",
@@ -2163,7 +2119,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(1),
rn: vreg(12),
rm: vreg(28),
ty: I16X8,
size: VectorSize::Size16x8,
},
"810D7C6E",
"uqadd v1.8h, v12.8h, v28.8h",
@@ -2175,7 +2131,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(12),
rn: vreg(2),
rm: vreg(6),
ty: I32X4,
size: VectorSize::Size32x4,
},
"4C0CA66E",
"uqadd v12.4s, v2.4s, v6.4s",
@@ -2187,7 +2143,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(20),
rn: vreg(7),
rm: vreg(13),
ty: I64X2,
size: VectorSize::Size64x2,
},
"F40CED6E",
"uqadd v20.2d, v7.2d, v13.2d",
@@ -2199,7 +2155,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(1),
rn: vreg(2),
rm: vreg(8),
ty: I8X16,
size: VectorSize::Size8x16,
},
"412C286E",
"uqsub v1.16b, v2.16b, v8.16b",
@@ -2211,7 +2167,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(1),
rn: vreg(12),
rm: vreg(28),
ty: I16X8,
size: VectorSize::Size16x8,
},
"812D7C6E",
"uqsub v1.8h, v12.8h, v28.8h",
@@ -2223,7 +2179,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(12),
rn: vreg(2),
rm: vreg(6),
ty: I32X4,
size: VectorSize::Size32x4,
},
"4C2CA66E",
"uqsub v12.4s, v2.4s, v6.4s",
@@ -2235,7 +2191,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(20),
rn: vreg(7),
rm: vreg(13),
ty: I64X2,
size: VectorSize::Size64x2,
},
"F42CED6E",
"uqsub v20.2d, v7.2d, v13.2d",
@@ -2247,7 +2203,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(3),
rn: vreg(23),
rm: vreg(24),
ty: I8X16,
size: VectorSize::Size8x16,
},
"E38E386E",
"cmeq v3.16b, v23.16b, v24.16b",
@@ -2259,7 +2215,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(3),
rn: vreg(23),
rm: vreg(24),
ty: I8X16,
size: VectorSize::Size8x16,
},
"E336384E",
"cmgt v3.16b, v23.16b, v24.16b",
@@ -2271,7 +2227,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(23),
rn: vreg(9),
rm: vreg(12),
ty: I8X16,
size: VectorSize::Size8x16,
},
"373D2C4E",
"cmge v23.16b, v9.16b, v12.16b",
@@ -2283,7 +2239,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(5),
rn: vreg(1),
rm: vreg(1),
ty: I8X16,
size: VectorSize::Size8x16,
},
"2534216E",
"cmhi v5.16b, v1.16b, v1.16b",
@@ -2295,7 +2251,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(8),
rn: vreg(2),
rm: vreg(15),
ty: I8X16,
size: VectorSize::Size8x16,
},
"483C2F6E",
"cmhs v8.16b, v2.16b, v15.16b",
@@ -2307,7 +2263,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(3),
rn: vreg(23),
rm: vreg(24),
ty: I16X8,
size: VectorSize::Size16x8,
},
"E38E786E",
"cmeq v3.8h, v23.8h, v24.8h",
@@ -2319,7 +2275,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(3),
rn: vreg(23),
rm: vreg(24),
ty: I16X8,
size: VectorSize::Size16x8,
},
"E336784E",
"cmgt v3.8h, v23.8h, v24.8h",
@@ -2331,7 +2287,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(23),
rn: vreg(9),
rm: vreg(12),
ty: I16X8,
size: VectorSize::Size16x8,
},
"373D6C4E",
"cmge v23.8h, v9.8h, v12.8h",
@@ -2343,7 +2299,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(5),
rn: vreg(1),
rm: vreg(1),
ty: I16X8,
size: VectorSize::Size16x8,
},
"2534616E",
"cmhi v5.8h, v1.8h, v1.8h",
@@ -2355,7 +2311,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(8),
rn: vreg(2),
rm: vreg(15),
ty: I16X8,
size: VectorSize::Size16x8,
},
"483C6F6E",
"cmhs v8.8h, v2.8h, v15.8h",
@@ -2367,7 +2323,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(3),
rn: vreg(23),
rm: vreg(24),
ty: I32X4,
size: VectorSize::Size32x4,
},
"E38EB86E",
"cmeq v3.4s, v23.4s, v24.4s",
@@ -2379,7 +2335,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(3),
rn: vreg(23),
rm: vreg(24),
ty: I32X4,
size: VectorSize::Size32x4,
},
"E336B84E",
"cmgt v3.4s, v23.4s, v24.4s",
@@ -2391,7 +2347,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(23),
rn: vreg(9),
rm: vreg(12),
ty: I32X4,
size: VectorSize::Size32x4,
},
"373DAC4E",
"cmge v23.4s, v9.4s, v12.4s",
@@ -2403,7 +2359,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(5),
rn: vreg(1),
rm: vreg(1),
ty: I32X4,
size: VectorSize::Size32x4,
},
"2534A16E",
"cmhi v5.4s, v1.4s, v1.4s",
@@ -2415,7 +2371,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(8),
rn: vreg(2),
rm: vreg(15),
ty: I32X4,
size: VectorSize::Size32x4,
},
"483CAF6E",
"cmhs v8.4s, v2.4s, v15.4s",
@@ -2427,7 +2383,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(28),
rn: vreg(12),
rm: vreg(4),
ty: F32X4,
size: VectorSize::Size32x4,
},
"9CE5244E",
"fcmeq v28.4s, v12.4s, v4.4s",
@@ -2439,7 +2395,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(3),
rn: vreg(16),
rm: vreg(31),
ty: F64X2,
size: VectorSize::Size64x2,
},
"03E6FF6E",
"fcmgt v3.2d, v16.2d, v31.2d",
@@ -2451,7 +2407,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(18),
rn: vreg(23),
rm: vreg(0),
ty: F64X2,
size: VectorSize::Size64x2,
},
"F2E6606E",
"fcmge v18.2d, v23.2d, v0.2d",
@@ -2463,7 +2419,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(20),
rn: vreg(19),
rm: vreg(18),
ty: I32X4,
size: VectorSize::Size32x4,
},
"741E324E",
"and v20.16b, v19.16b, v18.16b",
@@ -2475,7 +2431,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(8),
rn: vreg(11),
rm: vreg(1),
ty: I8X16,
size: VectorSize::Size8x16,
},
"681D614E",
"bic v8.16b, v11.16b, v1.16b",
@@ -2487,7 +2443,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(15),
rn: vreg(2),
rm: vreg(12),
ty: I16X8,
size: VectorSize::Size16x8,
},
"4F1CAC4E",
"orr v15.16b, v2.16b, v12.16b",
@@ -2499,7 +2455,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(18),
rn: vreg(3),
rm: vreg(22),
ty: I8X16,
size: VectorSize::Size8x16,
},
"721C366E",
"eor v18.16b, v3.16b, v22.16b",
@@ -2511,7 +2467,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(8),
rn: vreg(9),
rm: vreg(1),
ty: I8X16,
size: VectorSize::Size8x16,
},
"281D616E",
"bsl v8.16b, v9.16b, v1.16b",
@@ -2523,7 +2479,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(8),
rn: vreg(12),
rm: vreg(1),
ty: I8X16,
size: VectorSize::Size8x16,
},
"88A5216E",
"umaxp v8.16b, v12.16b, v1.16b",
@@ -2535,7 +2491,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(1),
rn: vreg(6),
rm: vreg(1),
ty: I16X8,
size: VectorSize::Size16x8,
},
"C1A4616E",
"umaxp v1.8h, v6.8h, v1.8h",
@@ -2547,7 +2503,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(1),
rn: vreg(20),
rm: vreg(16),
ty: I32X4,
size: VectorSize::Size32x4,
},
"81A6B06E",
"umaxp v1.4s, v20.4s, v16.4s",
@@ -2559,7 +2515,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(5),
rn: vreg(1),
rm: vreg(1),
ty: I8X16,
size: VectorSize::Size8x16,
},
"2584214E",
"add v5.16b, v1.16b, v1.16b",
@@ -2571,7 +2527,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(7),
rn: vreg(13),
rm: vreg(2),
ty: I16X8,
size: VectorSize::Size16x8,
},
"A785624E",
"add v7.8h, v13.8h, v2.8h",
@@ -2583,7 +2539,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(18),
rn: vreg(9),
rm: vreg(6),
ty: I32X4,
size: VectorSize::Size32x4,
},
"3285A64E",
"add v18.4s, v9.4s, v6.4s",
@@ -2595,7 +2551,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(1),
rn: vreg(3),
rm: vreg(2),
ty: I64X2,
size: VectorSize::Size64x2,
},
"6184E24E",
"add v1.2d, v3.2d, v2.2d",
@@ -2607,7 +2563,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(5),
rn: vreg(1),
rm: vreg(1),
ty: I8X16,
size: VectorSize::Size8x16,
},
"2584216E",
"sub v5.16b, v1.16b, v1.16b",
@@ -2619,7 +2575,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(7),
rn: vreg(13),
rm: vreg(2),
ty: I16X8,
size: VectorSize::Size16x8,
},
"A785626E",
"sub v7.8h, v13.8h, v2.8h",
@@ -2631,7 +2587,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(18),
rn: vreg(9),
rm: vreg(6),
ty: I32X4,
size: VectorSize::Size32x4,
},
"3285A66E",
"sub v18.4s, v9.4s, v6.4s",
@@ -2643,7 +2599,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(18),
rn: vreg(0),
rm: vreg(8),
ty: I64X2,
size: VectorSize::Size64x2,
},
"1284E86E",
"sub v18.2d, v0.2d, v8.2d",
@@ -2655,7 +2611,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(25),
rn: vreg(9),
rm: vreg(8),
ty: I8X16,
size: VectorSize::Size8x16,
},
"399D284E",
"mul v25.16b, v9.16b, v8.16b",
@@ -2667,7 +2623,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(30),
rn: vreg(30),
rm: vreg(12),
ty: I16X8,
size: VectorSize::Size16x8,
},
"DE9F6C4E",
"mul v30.8h, v30.8h, v12.8h",
@@ -2679,7 +2635,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(18),
rn: vreg(18),
rm: vreg(18),
ty: I32X4,
size: VectorSize::Size32x4,
},
"529EB24E",
"mul v18.4s, v18.4s, v18.4s",
@@ -2691,7 +2647,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(18),
rn: vreg(18),
rm: vreg(18),
ty: I8X16,
size: VectorSize::Size8x16,
},
"5246326E",
"ushl v18.16b, v18.16b, v18.16b",
@@ -2703,7 +2659,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(18),
rn: vreg(18),
rm: vreg(18),
ty: I16X8,
size: VectorSize::Size16x8,
},
"5246726E",
"ushl v18.8h, v18.8h, v18.8h",
@@ -2715,7 +2671,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(18),
rn: vreg(1),
rm: vreg(21),
ty: I32X4,
size: VectorSize::Size32x4,
},
"3244B56E",
"ushl v18.4s, v1.4s, v21.4s",
@@ -2727,7 +2683,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(5),
rn: vreg(7),
rm: vreg(19),
ty: I64X2,
size: VectorSize::Size64x2,
},
"E544F36E",
"ushl v5.2d, v7.2d, v19.2d",
@@ -2739,7 +2695,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(18),
rn: vreg(18),
rm: vreg(18),
ty: I8X16,
size: VectorSize::Size8x16,
},
"5246324E",
"sshl v18.16b, v18.16b, v18.16b",
@@ -2751,7 +2707,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(30),
rn: vreg(1),
rm: vreg(29),
ty: I16X8,
size: VectorSize::Size16x8,
},
"3E447D4E",
"sshl v30.8h, v1.8h, v29.8h",
@@ -2763,7 +2719,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(8),
rn: vreg(22),
rm: vreg(21),
ty: I32X4,
size: VectorSize::Size32x4,
},
"C846B54E",
"sshl v8.4s, v22.4s, v21.4s",
@@ -2775,7 +2731,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(8),
rn: vreg(22),
rm: vreg(2),
ty: I64X2,
size: VectorSize::Size64x2,
},
"C846E24E",
"sshl v8.2d, v22.2d, v2.2d",
@@ -2786,7 +2742,7 @@ fn test_aarch64_binemit() {
op: VecMisc2::Not,
rd: writable_vreg(2),
rn: vreg(1),
ty: I32X4,
size: VectorSize::Size32x4,
},
"2258206E",
"mvn v2.16b, v1.16b",
@@ -2797,7 +2753,7 @@ fn test_aarch64_binemit() {
op: VecMisc2::Neg,
rd: writable_vreg(8),
rn: vreg(12),
ty: I8X16,
size: VectorSize::Size8x16,
},
"88B9206E",
"neg v8.16b, v12.16b",
@@ -2808,7 +2764,7 @@ fn test_aarch64_binemit() {
op: VecMisc2::Neg,
rd: writable_vreg(0),
rn: vreg(31),
ty: I16X8,
size: VectorSize::Size16x8,
},
"E0BB606E",
"neg v0.8h, v31.8h",
@@ -2819,7 +2775,7 @@ fn test_aarch64_binemit() {
op: VecMisc2::Neg,
rd: writable_vreg(2),
rn: vreg(3),
ty: I32X4,
size: VectorSize::Size32x4,
},
"62B8A06E",
"neg v2.4s, v3.4s",
@@ -2830,7 +2786,7 @@ fn test_aarch64_binemit() {
op: VecMisc2::Neg,
rd: writable_vreg(10),
rn: vreg(8),
ty: I64X2,
size: VectorSize::Size64x2,
},
"0AB9E06E",
"neg v10.2d, v8.2d",
@@ -2841,7 +2797,7 @@ fn test_aarch64_binemit() {
op: VecLanesOp::Uminv,
rd: writable_vreg(2),
rn: vreg(1),
ty: I8X16,
size: VectorSize::Size8x16,
},
"22A8316E",
"uminv b2, v1.16b",
@@ -2852,7 +2808,7 @@ fn test_aarch64_binemit() {
op: VecLanesOp::Uminv,
rd: writable_vreg(3),
rn: vreg(11),
ty: I16X8,
size: VectorSize::Size16x8,
},
"63A9716E",
"uminv h3, v11.8h",
@@ -2863,7 +2819,7 @@ fn test_aarch64_binemit() {
op: VecLanesOp::Uminv,
rd: writable_vreg(18),
rn: vreg(4),
ty: I32X4,
size: VectorSize::Size32x4,
},
"92A8B16E",
"uminv s18, v4.4s",
@@ -3214,7 +3170,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(1),
rn: vreg(30),
idx: 2,
size: ScalarSize::Size32,
size: VectorSize::Size32x4,
},
"C107145E",
"mov s1, v30.s[2]",
@@ -3225,7 +3181,7 @@ fn test_aarch64_binemit() {
rd: writable_vreg(23),
rn: vreg(11),
idx: 0,
size: ScalarSize::Size64,
size: VectorSize::Size64x2,
},
"7705085E",
"mov d23, v11.d[0]",
@@ -3443,6 +3399,50 @@ fn test_aarch64_binemit() {
"fmin d15, d30, d31",
));
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Uqadd64,
rd: writable_vreg(21),
rn: vreg(22),
rm: vreg(23),
},
"D50EF77E",
"uqadd d21, d22, d23",
));
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Sqadd64,
rd: writable_vreg(21),
rn: vreg(22),
rm: vreg(23),
},
"D50EF75E",
"sqadd d21, d22, d23",
));
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Uqsub64,
rd: writable_vreg(21),
rn: vreg(22),
rm: vreg(23),
},
"D52EF77E",
"uqsub d21, d22, d23",
));
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Sqsub64,
rd: writable_vreg(21),
rn: vreg(22),
rm: vreg(23),
},
"D52EF75E",
"sqsub d21, d22, d23",
));
insns.push((
Inst::FpuRRRR {
fpu_op: FPUOp3::MAdd32,