s390x: clean up lower.rs (#4355)
Now that lowering is fully done in ISLE, clean up some code remnants in lower.rs. In particular, move code to lower/isle.rs where possible, and inline lower_insn_to_regs into its caller and simplify.
This commit is contained in:
Ulrich Weigand
@@ -1,329 +1,15 @@
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//! Lowering rules for S390x.
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//! Lowering rules for S390x.
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use crate::ir::condcodes::IntCC;
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use crate::ir::Inst as IRInst;
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use crate::ir::Inst as IRInst;
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use crate::ir::{MemFlags, Opcode};
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use crate::ir::Opcode;
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use crate::isa::s390x::abi::*;
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use crate::isa::s390x::inst::Inst;
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use crate::isa::s390x::inst::*;
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use crate::isa::s390x::settings as s390x_settings;
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use crate::isa::s390x::S390xBackend;
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use crate::isa::s390x::S390xBackend;
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use crate::machinst::lower::*;
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use crate::machinst::{InsnOutput, LowerBackend, LowerCtx, MachLabel};
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use crate::machinst::*;
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use crate::settings::Flags;
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use crate::CodegenResult;
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use crate::CodegenResult;
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use smallvec::SmallVec;
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use smallvec::SmallVec;
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pub mod isle;
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pub mod isle;
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//============================================================================
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// Lowering: force instruction input into a register
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/// Sign-extend the low `from_bits` bits of `value` to a full u64.
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fn sign_extend_to_u64(value: u64, from_bits: u8) -> u64 {
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assert!(from_bits <= 64);
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if from_bits >= 64 {
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value
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} else {
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(((value << (64 - from_bits)) as i64) >> (64 - from_bits)) as u64
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}
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}
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//=============================================================================
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// Lowering: comparisons
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/// Determines whether this condcode interprets inputs as signed or
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/// unsigned. See the documentation for the `icmp` instruction in
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/// cranelift-codegen/meta/src/shared/instructions.rs for further insights
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/// into this.
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pub fn condcode_is_signed(cc: IntCC) -> bool {
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match cc {
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IntCC::Equal => false,
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IntCC::NotEqual => false,
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IntCC::SignedGreaterThanOrEqual => true,
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IntCC::SignedGreaterThan => true,
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IntCC::SignedLessThanOrEqual => true,
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IntCC::SignedLessThan => true,
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IntCC::UnsignedGreaterThanOrEqual => false,
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IntCC::UnsignedGreaterThan => false,
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IntCC::UnsignedLessThanOrEqual => false,
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IntCC::UnsignedLessThan => false,
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IntCC::Overflow => true,
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IntCC::NotOverflow => true,
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}
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}
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//============================================================================
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// Lowering: main entry point for lowering a instruction
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fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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ctx: &mut C,
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insn: IRInst,
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flags: &Flags,
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isa_flags: &s390x_settings::Flags,
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) -> CodegenResult<()> {
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let op = ctx.data(insn).opcode();
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let outputs: SmallVec<[InsnOutput; 2]> = (0..ctx.num_outputs(insn))
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.map(|i| InsnOutput { insn, output: i })
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.collect();
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let ty = if outputs.len() > 0 {
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Some(ctx.output_ty(insn, 0))
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} else {
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None
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};
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if let Ok(()) = super::lower::isle::lower(ctx, flags, isa_flags, &outputs, insn) {
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return Ok(());
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}
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let implemented_in_isle = || {
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unreachable!(
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"implemented in ISLE: inst = `{}`, type = `{:?}`",
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ctx.dfg().display_inst(insn),
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ty
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);
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};
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match op {
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Opcode::Nop
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| Opcode::Copy
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| Opcode::Iconst
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| Opcode::Bconst
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| Opcode::F32const
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| Opcode::F64const
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| Opcode::Null
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| Opcode::Iadd
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| Opcode::IaddIfcout
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| Opcode::Isub
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| Opcode::Iabs
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| Opcode::Ineg
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| Opcode::Imul
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| Opcode::Umulhi
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| Opcode::Smulhi
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| Opcode::Udiv
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| Opcode::Urem
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| Opcode::Sdiv
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| Opcode::Srem
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| Opcode::Ishl
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| Opcode::Ushr
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| Opcode::Sshr
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| Opcode::Rotr
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| Opcode::Rotl
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| Opcode::Ireduce
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| Opcode::Uextend
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| Opcode::Sextend
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| Opcode::Bnot
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| Opcode::Band
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| Opcode::Bor
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| Opcode::Bxor
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| Opcode::BandNot
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| Opcode::BorNot
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| Opcode::BxorNot
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| Opcode::Bitselect
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| Opcode::Breduce
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| Opcode::Bextend
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| Opcode::Bmask
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| Opcode::Bint
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| Opcode::Clz
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| Opcode::Cls
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| Opcode::Ctz
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| Opcode::Popcnt
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| Opcode::Fadd
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| Opcode::Fsub
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| Opcode::Fmul
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| Opcode::Fdiv
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| Opcode::Fmin
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| Opcode::Fmax
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| Opcode::Sqrt
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| Opcode::Fneg
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| Opcode::Fabs
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| Opcode::Fpromote
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| Opcode::Fdemote
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| Opcode::Ceil
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| Opcode::Floor
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| Opcode::Trunc
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| Opcode::Nearest
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| Opcode::Fma
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| Opcode::Fcopysign
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| Opcode::FcvtFromUint
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| Opcode::FcvtFromSint
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| Opcode::FcvtToUint
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| Opcode::FcvtToSint
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| Opcode::FcvtToUintSat
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| Opcode::FcvtToSintSat
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| Opcode::Bitcast
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| Opcode::Load
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| Opcode::Uload8
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| Opcode::Sload8
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| Opcode::Uload16
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| Opcode::Sload16
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| Opcode::Uload32
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| Opcode::Sload32
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| Opcode::Store
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| Opcode::Istore8
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| Opcode::Istore16
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| Opcode::Istore32
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| Opcode::AtomicRmw
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| Opcode::AtomicCas
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| Opcode::AtomicLoad
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| Opcode::AtomicStore
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| Opcode::Fence
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| Opcode::Icmp
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| Opcode::Fcmp
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| Opcode::IsNull
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| Opcode::IsInvalid
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| Opcode::Select
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| Opcode::SelectifSpectreGuard
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| Opcode::Trap
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| Opcode::ResumableTrap
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| Opcode::Trapz
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| Opcode::Trapnz
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| Opcode::ResumableTrapnz
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| Opcode::Trapif
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| Opcode::Debugtrap
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| Opcode::Call
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| Opcode::CallIndirect
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| Opcode::FallthroughReturn
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| Opcode::Return
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| Opcode::StackAddr
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| Opcode::FuncAddr
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| Opcode::SymbolValue => implemented_in_isle(),
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Opcode::UaddSat | Opcode::SaddSat => unimplemented!(),
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Opcode::UsubSat | Opcode::SsubSat => unimplemented!(),
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Opcode::Bitrev => unimplemented!(),
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Opcode::FcvtLowFromSint => unimplemented!("FcvtLowFromSint"),
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Opcode::StackLoad | Opcode::StackStore => {
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panic!("Direct stack memory access not supported; should not be used by Wasm");
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}
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Opcode::ConstAddr => unimplemented!(),
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Opcode::HeapAddr => {
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panic!("heap_addr should have been removed by legalization!");
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}
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Opcode::TableAddr => {
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panic!("table_addr should have been removed by legalization!");
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}
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Opcode::GlobalValue => {
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panic!("global_value should have been removed by legalization!");
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}
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Opcode::TlsValue => {
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unimplemented!("Thread-local storage support not implemented!");
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}
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Opcode::GetPinnedReg | Opcode::SetPinnedReg => {
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unimplemented!("Pinned register support not implemented!");
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}
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Opcode::RawBitcast
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| Opcode::Splat
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| Opcode::Swizzle
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| Opcode::Insertlane
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| Opcode::Extractlane
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| Opcode::Imin
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| Opcode::Umin
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| Opcode::Imax
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| Opcode::Umax
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| Opcode::AvgRound
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| Opcode::FminPseudo
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| Opcode::FmaxPseudo
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| Opcode::Uload8x8
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| Opcode::Sload8x8
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| Opcode::Uload16x4
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| Opcode::Sload16x4
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| Opcode::Uload32x2
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| Opcode::Sload32x2
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| Opcode::Vconst
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| Opcode::Shuffle
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| Opcode::Vsplit
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| Opcode::Vconcat
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| Opcode::Vselect
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| Opcode::VanyTrue
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| Opcode::VallTrue
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| Opcode::VhighBits
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| Opcode::ScalarToVector
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| Opcode::Snarrow
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| Opcode::Unarrow
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| Opcode::Uunarrow
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| Opcode::SwidenLow
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| Opcode::SwidenHigh
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| Opcode::UwidenLow
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| Opcode::UwidenHigh
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| Opcode::WideningPairwiseDotProductS
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| Opcode::SqmulRoundSat
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| Opcode::FvpromoteLow
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| Opcode::Fvdemote
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| Opcode::IaddPairwise => {
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// TODO
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unimplemented!("Vector ops not implemented.");
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}
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Opcode::Isplit | Opcode::Iconcat => unimplemented!("Wide integer ops not implemented."),
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Opcode::IfcmpSp => {
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panic!("Unused opcode should not be encountered.");
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}
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Opcode::Ifcmp
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| Opcode::Ffcmp
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| Opcode::Trapff
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| Opcode::Trueif
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| Opcode::Trueff
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| Opcode::Selectif => {
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panic!("Flags opcode should not be encountered.");
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}
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Opcode::Jump
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| Opcode::Brz
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| Opcode::Brnz
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| Opcode::BrIcmp
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| Opcode::Brif
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| Opcode::Brff
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| Opcode::BrTable => {
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panic!("Branch opcode reached non-branch lowering logic!");
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}
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Opcode::IaddImm
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| Opcode::ImulImm
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| Opcode::UdivImm
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| Opcode::SdivImm
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| Opcode::UremImm
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| Opcode::SremImm
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| Opcode::IrsubImm
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| Opcode::IaddCin
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| Opcode::IaddIfcin
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| Opcode::IaddCout
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| Opcode::IaddCarry
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| Opcode::IaddIfcarry
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| Opcode::IsubBin
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| Opcode::IsubIfbin
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||||||
| Opcode::IsubBout
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| Opcode::IsubIfbout
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| Opcode::IsubBorrow
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||||||
| Opcode::IsubIfborrow
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| Opcode::BandImm
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||||||
| Opcode::BorImm
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| Opcode::BxorImm
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||||||
| Opcode::RotlImm
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| Opcode::RotrImm
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| Opcode::IshlImm
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| Opcode::UshrImm
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||||||
| Opcode::SshrImm
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||||||
| Opcode::IcmpImm
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||||||
| Opcode::IfcmpImm => {
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panic!("ALU+imm and ALU+carry ops should not appear here!");
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}
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}
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Ok(())
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}
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//=============================================================================
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//=============================================================================
|
||||||
// Lowering-backend trait implementation.
|
// Lowering-backend trait implementation.
|
||||||
|
|
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@@ -331,7 +17,255 @@ impl LowerBackend for S390xBackend {
|
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type MInst = Inst;
|
type MInst = Inst;
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|
|
||||||
fn lower<C: LowerCtx<I = Inst>>(&self, ctx: &mut C, ir_inst: IRInst) -> CodegenResult<()> {
|
fn lower<C: LowerCtx<I = Inst>>(&self, ctx: &mut C, ir_inst: IRInst) -> CodegenResult<()> {
|
||||||
lower_insn_to_regs(ctx, ir_inst, &self.flags, &self.isa_flags)
|
let op = ctx.data(ir_inst).opcode();
|
||||||
|
let outputs: SmallVec<[InsnOutput; 2]> = (0..ctx.num_outputs(ir_inst))
|
||||||
|
.map(|i| InsnOutput {
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||||||
|
insn: ir_inst,
|
||||||
|
output: i,
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||||||
|
})
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||||||
|
.collect();
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||||||
|
let ty = if outputs.len() > 0 {
|
||||||
|
Some(ctx.output_ty(ir_inst, 0))
|
||||||
|
} else {
|
||||||
|
None
|
||||||
|
};
|
||||||
|
|
||||||
|
if let Ok(()) =
|
||||||
|
super::lower::isle::lower(ctx, &self.flags, &self.isa_flags, &outputs, ir_inst)
|
||||||
|
{
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||||||
|
return Ok(());
|
||||||
|
}
|
||||||
|
|
||||||
|
match op {
|
||||||
|
Opcode::Nop
|
||||||
|
| Opcode::Copy
|
||||||
|
| Opcode::Iconst
|
||||||
|
| Opcode::Bconst
|
||||||
|
| Opcode::F32const
|
||||||
|
| Opcode::F64const
|
||||||
|
| Opcode::Null
|
||||||
|
| Opcode::Iadd
|
||||||
|
| Opcode::IaddIfcout
|
||||||
|
| Opcode::Isub
|
||||||
|
| Opcode::Iabs
|
||||||
|
| Opcode::Ineg
|
||||||
|
| Opcode::Imul
|
||||||
|
| Opcode::Umulhi
|
||||||
|
| Opcode::Smulhi
|
||||||
|
| Opcode::Udiv
|
||||||
|
| Opcode::Urem
|
||||||
|
| Opcode::Sdiv
|
||||||
|
| Opcode::Srem
|
||||||
|
| Opcode::Ishl
|
||||||
|
| Opcode::Ushr
|
||||||
|
| Opcode::Sshr
|
||||||
|
| Opcode::Rotr
|
||||||
|
| Opcode::Rotl
|
||||||
|
| Opcode::Ireduce
|
||||||
|
| Opcode::Uextend
|
||||||
|
| Opcode::Sextend
|
||||||
|
| Opcode::Bnot
|
||||||
|
| Opcode::Band
|
||||||
|
| Opcode::Bor
|
||||||
|
| Opcode::Bxor
|
||||||
|
| Opcode::BandNot
|
||||||
|
| Opcode::BorNot
|
||||||
|
| Opcode::BxorNot
|
||||||
|
| Opcode::Bitselect
|
||||||
|
| Opcode::Breduce
|
||||||
|
| Opcode::Bextend
|
||||||
|
| Opcode::Bmask
|
||||||
|
| Opcode::Bint
|
||||||
|
| Opcode::Clz
|
||||||
|
| Opcode::Cls
|
||||||
|
| Opcode::Ctz
|
||||||
|
| Opcode::Popcnt
|
||||||
|
| Opcode::Fadd
|
||||||
|
| Opcode::Fsub
|
||||||
|
| Opcode::Fmul
|
||||||
|
| Opcode::Fdiv
|
||||||
|
| Opcode::Fmin
|
||||||
|
| Opcode::Fmax
|
||||||
|
| Opcode::Sqrt
|
||||||
|
| Opcode::Fneg
|
||||||
|
| Opcode::Fabs
|
||||||
|
| Opcode::Fpromote
|
||||||
|
| Opcode::Fdemote
|
||||||
|
| Opcode::Ceil
|
||||||
|
| Opcode::Floor
|
||||||
|
| Opcode::Trunc
|
||||||
|
| Opcode::Nearest
|
||||||
|
| Opcode::Fma
|
||||||
|
| Opcode::Fcopysign
|
||||||
|
| Opcode::FcvtFromUint
|
||||||
|
| Opcode::FcvtFromSint
|
||||||
|
| Opcode::FcvtToUint
|
||||||
|
| Opcode::FcvtToSint
|
||||||
|
| Opcode::FcvtToUintSat
|
||||||
|
| Opcode::FcvtToSintSat
|
||||||
|
| Opcode::Bitcast
|
||||||
|
| Opcode::Load
|
||||||
|
| Opcode::Uload8
|
||||||
|
| Opcode::Sload8
|
||||||
|
| Opcode::Uload16
|
||||||
|
| Opcode::Sload16
|
||||||
|
| Opcode::Uload32
|
||||||
|
| Opcode::Sload32
|
||||||
|
| Opcode::Store
|
||||||
|
| Opcode::Istore8
|
||||||
|
| Opcode::Istore16
|
||||||
|
| Opcode::Istore32
|
||||||
|
| Opcode::AtomicRmw
|
||||||
|
| Opcode::AtomicCas
|
||||||
|
| Opcode::AtomicLoad
|
||||||
|
| Opcode::AtomicStore
|
||||||
|
| Opcode::Fence
|
||||||
|
| Opcode::Icmp
|
||||||
|
| Opcode::Fcmp
|
||||||
|
| Opcode::IsNull
|
||||||
|
| Opcode::IsInvalid
|
||||||
|
| Opcode::Select
|
||||||
|
| Opcode::SelectifSpectreGuard
|
||||||
|
| Opcode::Trap
|
||||||
|
| Opcode::ResumableTrap
|
||||||
|
| Opcode::Trapz
|
||||||
|
| Opcode::Trapnz
|
||||||
|
| Opcode::ResumableTrapnz
|
||||||
|
| Opcode::Trapif
|
||||||
|
| Opcode::Debugtrap
|
||||||
|
| Opcode::Call
|
||||||
|
| Opcode::CallIndirect
|
||||||
|
| Opcode::FallthroughReturn
|
||||||
|
| Opcode::Return
|
||||||
|
| Opcode::StackAddr
|
||||||
|
| Opcode::FuncAddr
|
||||||
|
| Opcode::SymbolValue => {
|
||||||
|
unreachable!(
|
||||||
|
"implemented in ISLE: inst = `{}`, type = `{:?}`",
|
||||||
|
ctx.dfg().display_inst(ir_inst),
|
||||||
|
ty
|
||||||
|
)
|
||||||
|
}
|
||||||
|
|
||||||
|
Opcode::UaddSat
|
||||||
|
| Opcode::SaddSat
|
||||||
|
| Opcode::UsubSat
|
||||||
|
| Opcode::SsubSat
|
||||||
|
| Opcode::Bitrev
|
||||||
|
| Opcode::FcvtLowFromSint
|
||||||
|
| Opcode::ConstAddr
|
||||||
|
| Opcode::TlsValue
|
||||||
|
| Opcode::GetPinnedReg
|
||||||
|
| Opcode::SetPinnedReg
|
||||||
|
| Opcode::Isplit
|
||||||
|
| Opcode::Iconcat
|
||||||
|
| Opcode::RawBitcast
|
||||||
|
| Opcode::Splat
|
||||||
|
| Opcode::Swizzle
|
||||||
|
| Opcode::Insertlane
|
||||||
|
| Opcode::Extractlane
|
||||||
|
| Opcode::Imin
|
||||||
|
| Opcode::Umin
|
||||||
|
| Opcode::Imax
|
||||||
|
| Opcode::Umax
|
||||||
|
| Opcode::AvgRound
|
||||||
|
| Opcode::FminPseudo
|
||||||
|
| Opcode::FmaxPseudo
|
||||||
|
| Opcode::Uload8x8
|
||||||
|
| Opcode::Sload8x8
|
||||||
|
| Opcode::Uload16x4
|
||||||
|
| Opcode::Sload16x4
|
||||||
|
| Opcode::Uload32x2
|
||||||
|
| Opcode::Sload32x2
|
||||||
|
| Opcode::Vconst
|
||||||
|
| Opcode::Shuffle
|
||||||
|
| Opcode::Vsplit
|
||||||
|
| Opcode::Vconcat
|
||||||
|
| Opcode::Vselect
|
||||||
|
| Opcode::VanyTrue
|
||||||
|
| Opcode::VallTrue
|
||||||
|
| Opcode::VhighBits
|
||||||
|
| Opcode::ScalarToVector
|
||||||
|
| Opcode::Snarrow
|
||||||
|
| Opcode::Unarrow
|
||||||
|
| Opcode::Uunarrow
|
||||||
|
| Opcode::SwidenLow
|
||||||
|
| Opcode::SwidenHigh
|
||||||
|
| Opcode::UwidenLow
|
||||||
|
| Opcode::UwidenHigh
|
||||||
|
| Opcode::WideningPairwiseDotProductS
|
||||||
|
| Opcode::SqmulRoundSat
|
||||||
|
| Opcode::FvpromoteLow
|
||||||
|
| Opcode::Fvdemote
|
||||||
|
| Opcode::IaddPairwise => {
|
||||||
|
unreachable!(
|
||||||
|
"TODO: not yet implemented in ISLE: inst = `{}`, type = `{:?}`",
|
||||||
|
ctx.dfg().display_inst(ir_inst),
|
||||||
|
ty
|
||||||
|
)
|
||||||
|
}
|
||||||
|
|
||||||
|
Opcode::StackLoad | Opcode::StackStore => {
|
||||||
|
panic!("Direct stack memory access not supported; should not be used by Wasm");
|
||||||
|
}
|
||||||
|
Opcode::HeapAddr => {
|
||||||
|
panic!("heap_addr should have been removed by legalization!");
|
||||||
|
}
|
||||||
|
Opcode::TableAddr => {
|
||||||
|
panic!("table_addr should have been removed by legalization!");
|
||||||
|
}
|
||||||
|
Opcode::GlobalValue => {
|
||||||
|
panic!("global_value should have been removed by legalization!");
|
||||||
|
}
|
||||||
|
Opcode::Ifcmp
|
||||||
|
| Opcode::IfcmpSp
|
||||||
|
| Opcode::Ffcmp
|
||||||
|
| Opcode::Trapff
|
||||||
|
| Opcode::Trueif
|
||||||
|
| Opcode::Trueff
|
||||||
|
| Opcode::Selectif => {
|
||||||
|
panic!("Flags opcode should not be encountered.");
|
||||||
|
}
|
||||||
|
Opcode::Jump
|
||||||
|
| Opcode::Brz
|
||||||
|
| Opcode::Brnz
|
||||||
|
| Opcode::BrIcmp
|
||||||
|
| Opcode::Brif
|
||||||
|
| Opcode::Brff
|
||||||
|
| Opcode::BrTable => {
|
||||||
|
panic!("Branch opcode reached non-branch lowering logic!");
|
||||||
|
}
|
||||||
|
Opcode::IaddImm
|
||||||
|
| Opcode::ImulImm
|
||||||
|
| Opcode::UdivImm
|
||||||
|
| Opcode::SdivImm
|
||||||
|
| Opcode::UremImm
|
||||||
|
| Opcode::SremImm
|
||||||
|
| Opcode::IrsubImm
|
||||||
|
| Opcode::IaddCin
|
||||||
|
| Opcode::IaddIfcin
|
||||||
|
| Opcode::IaddCout
|
||||||
|
| Opcode::IaddCarry
|
||||||
|
| Opcode::IaddIfcarry
|
||||||
|
| Opcode::IsubBin
|
||||||
|
| Opcode::IsubIfbin
|
||||||
|
| Opcode::IsubBout
|
||||||
|
| Opcode::IsubIfbout
|
||||||
|
| Opcode::IsubBorrow
|
||||||
|
| Opcode::IsubIfborrow
|
||||||
|
| Opcode::BandImm
|
||||||
|
| Opcode::BorImm
|
||||||
|
| Opcode::BxorImm
|
||||||
|
| Opcode::RotlImm
|
||||||
|
| Opcode::RotrImm
|
||||||
|
| Opcode::IshlImm
|
||||||
|
| Opcode::UshrImm
|
||||||
|
| Opcode::SshrImm
|
||||||
|
| Opcode::IcmpImm
|
||||||
|
| Opcode::IfcmpImm => {
|
||||||
|
panic!("ALU+imm and ALU+carry ops should not appear here!");
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
fn lower_branch_group<C: LowerCtx<I = Inst>>(
|
fn lower_branch_group<C: LowerCtx<I = Inst>>(
|
||||||
|
|||||||
@@ -4,17 +4,19 @@
|
|||||||
pub mod generated_code;
|
pub mod generated_code;
|
||||||
|
|
||||||
// Types that the generated ISLE code uses via `use super::*`.
|
// Types that the generated ISLE code uses via `use super::*`.
|
||||||
use super::{
|
use crate::isa::s390x::abi::S390xMachineDeps;
|
||||||
CallIndInfo, CallInfo, Cond, Inst as MInst, MachLabel, MemArg, MemFlags, Opcode, Reg,
|
use crate::isa::s390x::inst::{
|
||||||
S390xMachineDeps, UImm16Shifted, UImm32Shifted,
|
stack_reg, writable_gpr, zero_reg, CallIndInfo, CallInfo, Cond, Inst as MInst, MemArg,
|
||||||
|
UImm16Shifted, UImm32Shifted,
|
||||||
};
|
};
|
||||||
use crate::isa::s390x::settings::Flags as IsaFlags;
|
use crate::isa::s390x::settings::Flags as IsaFlags;
|
||||||
use crate::machinst::isle::*;
|
use crate::machinst::isle::*;
|
||||||
|
use crate::machinst::{MachLabel, Reg};
|
||||||
use crate::settings::Flags;
|
use crate::settings::Flags;
|
||||||
use crate::{
|
use crate::{
|
||||||
ir::{
|
ir::{
|
||||||
condcodes::*, immediates::*, types::*, AtomicRmwOp, Endianness, Inst, InstructionData,
|
condcodes::*, immediates::*, types::*, AtomicRmwOp, Endianness, Inst, InstructionData,
|
||||||
StackSlot, TrapCode, Value, ValueList,
|
MemFlags, Opcode, StackSlot, TrapCode, Value, ValueList,
|
||||||
},
|
},
|
||||||
isa::unwind::UnwindInst,
|
isa::unwind::UnwindInst,
|
||||||
machinst::{InsnOutput, LowerCtx, VCodeConstant, VCodeConstantData},
|
machinst::{InsnOutput, LowerCtx, VCodeConstant, VCodeConstantData},
|
||||||
@@ -150,12 +152,12 @@ where
|
|||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
fn writable_gpr(&mut self, regno: u8) -> WritableReg {
|
fn writable_gpr(&mut self, regno: u8) -> WritableReg {
|
||||||
super::writable_gpr(regno)
|
writable_gpr(regno)
|
||||||
}
|
}
|
||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
fn zero_reg(&mut self) -> Reg {
|
fn zero_reg(&mut self) -> Reg {
|
||||||
super::zero_reg()
|
zero_reg()
|
||||||
}
|
}
|
||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
@@ -282,10 +284,7 @@ where
|
|||||||
let inst = self.lower_ctx.dfg().value_def(val).inst()?;
|
let inst = self.lower_ctx.dfg().value_def(val).inst()?;
|
||||||
let constant = self.lower_ctx.get_constant(inst)?;
|
let constant = self.lower_ctx.get_constant(inst)?;
|
||||||
let ty = self.lower_ctx.output_ty(inst, 0);
|
let ty = self.lower_ctx.output_ty(inst, 0);
|
||||||
Some(super::sign_extend_to_u64(
|
Some(sign_extend_to_u64(constant, self.ty_bits(ty).unwrap()))
|
||||||
constant,
|
|
||||||
self.ty_bits(ty).unwrap(),
|
|
||||||
))
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
@@ -390,7 +389,7 @@ where
|
|||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
fn signed(&mut self, cc: &IntCC) -> Option<()> {
|
fn signed(&mut self, cc: &IntCC) -> Option<()> {
|
||||||
if super::condcode_is_signed(*cc) {
|
if condcode_is_signed(*cc) {
|
||||||
Some(())
|
Some(())
|
||||||
} else {
|
} else {
|
||||||
None
|
None
|
||||||
@@ -399,7 +398,7 @@ where
|
|||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
fn unsigned(&mut self, cc: &IntCC) -> Option<()> {
|
fn unsigned(&mut self, cc: &IntCC) -> Option<()> {
|
||||||
if !super::condcode_is_signed(*cc) {
|
if !condcode_is_signed(*cc) {
|
||||||
Some(())
|
Some(())
|
||||||
} else {
|
} else {
|
||||||
None
|
None
|
||||||
@@ -468,7 +467,7 @@ where
|
|||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
fn memarg_stack_off(&mut self, base: i64, off: i64) -> MemArg {
|
fn memarg_stack_off(&mut self, base: i64, off: i64) -> MemArg {
|
||||||
MemArg::reg_plus_off(super::stack_reg(), base + off, MemFlags::trusted())
|
MemArg::reg_plus_off(stack_reg(), base + off, MemFlags::trusted())
|
||||||
}
|
}
|
||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
@@ -555,3 +554,36 @@ where
|
|||||||
self.lower_ctx.emit(inst.clone());
|
self.lower_ctx.emit(inst.clone());
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/// Sign-extend the low `from_bits` bits of `value` to a full u64.
|
||||||
|
#[inline]
|
||||||
|
fn sign_extend_to_u64(value: u64, from_bits: u8) -> u64 {
|
||||||
|
assert!(from_bits <= 64);
|
||||||
|
if from_bits >= 64 {
|
||||||
|
value
|
||||||
|
} else {
|
||||||
|
(((value << (64 - from_bits)) as i64) >> (64 - from_bits)) as u64
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Determines whether this condcode interprets inputs as signed or
|
||||||
|
/// unsigned. See the documentation for the `icmp` instruction in
|
||||||
|
/// cranelift-codegen/meta/src/shared/instructions.rs for further insights
|
||||||
|
/// into this.
|
||||||
|
#[inline]
|
||||||
|
fn condcode_is_signed(cc: IntCC) -> bool {
|
||||||
|
match cc {
|
||||||
|
IntCC::Equal => false,
|
||||||
|
IntCC::NotEqual => false,
|
||||||
|
IntCC::SignedGreaterThanOrEqual => true,
|
||||||
|
IntCC::SignedGreaterThan => true,
|
||||||
|
IntCC::SignedLessThanOrEqual => true,
|
||||||
|
IntCC::SignedLessThan => true,
|
||||||
|
IntCC::UnsignedGreaterThanOrEqual => false,
|
||||||
|
IntCC::UnsignedGreaterThan => false,
|
||||||
|
IntCC::UnsignedLessThanOrEqual => false,
|
||||||
|
IntCC::UnsignedLessThan => false,
|
||||||
|
IntCC::Overflow => true,
|
||||||
|
IntCC::NotOverflow => true,
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|||||||
Reference in New Issue
Block a user