AArch64: port load and store operations to ISLE. (#4785)

This retains `lower_amode` in the handwritten code (@akirilov-arm
reports that there is an upcoming patch to port this), but tweaks it
slightly to take a `Value` rather than an `Inst`.

cranelift/filetests/filetests/isa/aarch64/amodes.clif

@@ -36,8 +36,8 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   mov w6, w0
-;   ldr w0, [x6, w1, UXTW]
+;   mov w5, w0
+;   ldr w0, [x5, w1, UXTW]
 ;   ret
 
 function %f8(i64, i32) -> i32 {
@@ -52,10 +52,10 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   add x6, x0, #68
-;   add x6, x6, x0
-;   add x6, x6, x1, SXTW
-;   ldr w0, [x6, w1, SXTW]
+;   add x5, x0, #68
+;   add x5, x5, x0
+;   add x5, x5, x1, SXTW
+;   ldr w0, [x5, w1, SXTW]
 ;   ret
 
 function %f9(i64, i64, i64) -> i32 {
@@ -85,10 +85,10 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movz x8, #4100
-;   add x8, x8, x1
-;   add x8, x8, x2
-;   ldr w0, [x8, x0]
+;   movz x7, #4100
+;   add x7, x7, x1
+;   add x7, x7, x2
+;   ldr w0, [x7, x0]
 ;   ret
 
 function %f10() -> i32 {
@@ -99,8 +99,8 @@ block0:
 }
 
 ; block0:
-;   movz x2, #1234
-;   ldr w0, [x2]
+;   movz x1, #1234
+;   ldr w0, [x1]
 ;   ret
 
 function %f11(i64) -> i32 {
@@ -112,8 +112,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   add x4, x0, #8388608
-;   ldr w0, [x4]
+;   add x3, x0, #8388608
+;   ldr w0, [x3]
 ;   ret
 
 function %f12(i64) -> i32 {
@@ -125,8 +125,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   sub x4, x0, #4
-;   ldr w0, [x4]
+;   sub x3, x0, #4
+;   ldr w0, [x3]
 ;   ret
 
 function %f13(i64) -> i32 {
@@ -138,10 +138,10 @@ block0(v0: i64):
 }
 
 ; block0:
-;   movz w4, #51712
-;   movk w4, #15258, LSL #16
-;   add x4, x4, x0
-;   ldr w0, [x4]
+;   movz w3, #51712
+;   movk w3, #15258, LSL #16
+;   add x3, x3, x0
+;   ldr w0, [x3]
 ;   ret
 
 function %f14(i32) -> i32 {
@@ -152,8 +152,8 @@ block0(v0: i32):
 }
 
 ; block0:
-;   sxtw x4, w0
-;   ldr w0, [x4]
+;   sxtw x3, w0
+;   ldr w0, [x3]
 ;   ret
 
 function %f15(i32, i32) -> i32 {
@@ -166,8 +166,8 @@ block0(v0: i32, v1: i32):
 }
 
 ; block0:
-;   sxtw x6, w0
-;   ldr w0, [x6, w1, SXTW]
+;   sxtw x5, w0
+;   ldr w0, [x5, w1, SXTW]
 ;   ret
 
 function %f18(i64, i64, i64) -> i32 {
@@ -179,8 +179,8 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movn w8, #4097
-;   ldrsh x0, [x8]
+;   movn w7, #4097
+;   ldrsh x0, [x7]
 ;   ret
 
 function %f19(i64, i64, i64) -> i32 {
@@ -192,8 +192,8 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movz x8, #4098
-;   ldrsh x0, [x8]
+;   movz x7, #4098
+;   ldrsh x0, [x7]
 ;   ret
 
 function %f20(i64, i64, i64) -> i32 {
@@ -205,9 +205,9 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movn w8, #4097
-;   sxtw x10, w8
-;   ldrsh x0, [x10]
+;   movn w7, #4097
+;   sxtw x9, w7
+;   ldrsh x0, [x9]
 ;   ret
 
 function %f21(i64, i64, i64) -> i32 {
@@ -219,9 +219,9 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   movz x8, #4098
-;   sxtw x10, w8
-;   ldrsh x0, [x10]
+;   movz x7, #4098
+;   sxtw x9, w7
+;   ldrsh x0, [x9]
 ;   ret
 
 function %i128(i64) -> i128 {
@@ -232,11 +232,11 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x8, x0
-;   ldp x3, x1, [x8]
-;   mov x11, x3
+;   mov x6, x0
+;   ldp x7, x1, [x6]
+;   mov x11, x7
 ;   stp x11, x1, [x0]
-;   mov x0, x3
+;   mov x0, x7
 ;   ret
 
 function %i128_imm_offset(i64) -> i128 {
@@ -247,11 +247,11 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x8, x0
-;   ldp x3, x1, [x8, #16]
-;   mov x11, x3
+;   mov x6, x0
+;   ldp x7, x1, [x6, #16]
+;   mov x11, x7
 ;   stp x11, x1, [x0, #16]
-;   mov x0, x3
+;   mov x0, x7
 ;   ret
 
 function %i128_imm_offset_large(i64) -> i128 {
@@ -262,11 +262,11 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x8, x0
-;   ldp x3, x1, [x8, #504]
-;   mov x11, x3
+;   mov x6, x0
+;   ldp x7, x1, [x6, #504]
+;   mov x11, x7
 ;   stp x11, x1, [x0, #504]
-;   mov x0, x3
+;   mov x0, x7
 ;   ret
 
 function %i128_imm_offset_negative_large(i64) -> i128 {
@@ -277,11 +277,11 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x8, x0
-;   ldp x3, x1, [x8, #-512]
-;   mov x11, x3
+;   mov x6, x0
+;   ldp x7, x1, [x6, #-512]
+;   mov x11, x7
 ;   stp x11, x1, [x0, #-512]
-;   mov x0, x3
+;   mov x0, x7
 ;   ret
 
 function %i128_add_offset(i64) -> i128 {
@@ -293,11 +293,11 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mov x8, x0
-;   ldp x3, x1, [x8, #32]
-;   mov x11, x3
+;   mov x6, x0
+;   ldp x7, x1, [x6, #32]
+;   mov x11, x7
 ;   stp x11, x1, [x0, #32]
-;   mov x0, x3
+;   mov x0, x7
 ;   ret
 
 function %i128_32bit_sextend_simple(i32) -> i128 {
@@ -309,11 +309,11 @@ block0(v0: i32):
 }
 
 ; block0:
-;   sxtw x8, w0
-;   ldp x4, x1, [x8]
-;   sxtw x9, w0
-;   mov x0, x4
-;   stp x0, x1, [x9]
+;   sxtw x6, w0
+;   ldp x10, x1, [x6]
+;   sxtw x7, w0
+;   mov x0, x10
+;   stp x0, x1, [x7]
 ;   ret
 
 function %i128_32bit_sextend(i64, i32) -> i128 {
@@ -327,13 +327,13 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   mov x10, x0
-;   add x10, x10, x1, SXTW
-;   ldp x6, x7, [x10, #24]
+;   mov x8, x0
+;   add x8, x8, x1, SXTW
+;   ldp x10, x11, [x8, #24]
 ;   add x0, x0, x1, SXTW
-;   mov x15, x6
-;   mov x1, x7
+;   mov x15, x10
+;   mov x1, x11
 ;   stp x15, x1, [x0, #24]
-;   mov x0, x6
+;   mov x0, x10
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/heap_addr.clif

@@ -15,15 +15,15 @@ block0(v0: i64, v1: i32):
 
 ; block0:
 ;   mov w10, w1
-;   ldr x5, [x0]
-;   mov x11, x5
+;   ldr x11, [x0]
+;   mov x11, x11
 ;   subs xzr, x10, x11
 ;   b.ls label1 ; b label2
 ; block1:
-;   add x13, x0, x1, UXTW
+;   add x12, x0, x1, UXTW
 ;   subs xzr, x10, x11
-;   movz x14, #0
-;   csel x0, x14, x13, hi
+;   movz x13, #0
+;   csel x0, x13, x12, hi
 ;   csdb
 ;   ret
 ; block2:

cranelift/filetests/filetests/isa/aarch64/simd-lane-access-compile.clif

@@ -98,8 +98,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   ldr w2, [x0]
-;   fmov s0, w2
+;   ldr w4, [x0]
+;   fmov s0, w4
 ;   ret
 
 function %load32_zero_int(i32) -> i32x4 {

cranelift/filetests/filetests/isa/aarch64/simd.clif

@@ -86,9 +86,9 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   ldrb w4, [x0]
+;   ldrb w8, [x0]
 ;   ld1r { v0.16b }, [x1]
-;   dup v1.16b, w4
+;   dup v1.16b, w8
 ;   ret
 
 function %f8(i64, i64) -> i8x16, i8x16 {
@@ -100,9 +100,9 @@ block0(v0: i64, v1: i64):
 }
 
 ; block0:
-;   ldrb w4, [x0]
-;   dup v0.16b, w4
-;   dup v1.16b, w4
+;   ldrb w8, [x0]
+;   dup v0.16b, w8
+;   dup v1.16b, w8
 ;   ret
 
 function %f9() -> i32x2 {