added Opcode flags methods
generate `is_branch`, `is_terminator`, `can_trap` methods for `enum Opcode`.
This commit is contained in:
committed by
Jakob Stoklund Olesen
parent
19ac05577c
commit
93aa2b456e
@@ -83,7 +83,7 @@ trap = Instruction(
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'trap', r"""
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Terminate execution unconditionally.
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""",
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is_terminator=True)
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is_terminator=True, can_trap=True)
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trapz = Instruction(
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'trapz', r"""
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@@ -91,7 +91,7 @@ trapz = Instruction(
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if ``c`` is non-zero, execution continues at the following instruction.
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""",
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ins=c)
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ins=c, can_trap=True)
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trapnz = Instruction(
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'trapnz', r"""
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@@ -99,7 +99,7 @@ trapnz = Instruction(
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if ``c`` is zero, execution continues at the following instruction.
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""",
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ins=c)
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ins=c, can_trap=True)
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rvals = Operand('rvals', VARIABLE_ARGS, doc='return values')
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@@ -111,7 +111,7 @@ x_return = Instruction(
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provided return values. The list of return values must match the
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function signature's return types.
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""",
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ins=rvals)
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ins=rvals, is_terminator=True)
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FN = Operand(
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'FN',
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@@ -366,7 +366,7 @@ udiv = Instruction(
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This operation traps if the divisor is zero.
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""",
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ins=(x, y), outs=a)
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ins=(x, y), outs=a, can_trap=True)
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sdiv = Instruction(
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'sdiv', r"""
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@@ -377,7 +377,7 @@ sdiv = Instruction(
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representable in :math:`B` bits two's complement. This only happens
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when :math:`x = -2^{B-1}, y = -1`.
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""",
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ins=(x, y), outs=a)
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ins=(x, y), outs=a, can_trap=True)
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urem = Instruction(
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'urem', """
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@@ -385,7 +385,7 @@ urem = Instruction(
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This operation traps if the divisor is zero.
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""",
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ins=(x, y), outs=a)
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ins=(x, y), outs=a, can_trap=True)
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srem = Instruction(
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'srem', """
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@@ -399,7 +399,7 @@ srem = Instruction(
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dividend. Should we add a ``smod`` instruction for the case where
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the result has the same sign as the divisor?
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""",
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ins=(x, y), outs=a)
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ins=(x, y), outs=a, can_trap=True)
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a = Operand('a', iB)
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x = Operand('x', iB)
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@@ -1136,7 +1136,7 @@ fcvt_to_uint = Instruction(
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The result type must have the same number of vector lanes as the input.
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""",
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ins=x, outs=a)
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ins=x, outs=a, can_trap=True)
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fcvt_to_sint = Instruction(
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'fcvt_to_sint', r"""
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@@ -1148,7 +1148,7 @@ fcvt_to_sint = Instruction(
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The result type must have the same number of vector lanes as the input.
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""",
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ins=x, outs=a)
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ins=x, outs=a, can_trap=True)
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x = Operand('x', Int)
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a = Operand('a', FloatTo)
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