x64: Lower extractlane, scalar_to_vector, and splat in ISLE (#4780)

Lower extractlane, scalar_to_vector and splat in ISLE.

This PR also makes some changes to the SinkableLoad api
* change the return type of sink_load to RegMem as there are more functions available for dealing with RegMem
* add reg_mem_to_reg_mem_imm and register it as an automatic conversion

cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif

@@ -74,8 +74,8 @@ block0(v0: i8):
 ; block0:
 ;   uninit  %xmm0
 ;   pinsrb  $0, %xmm0, %rdi, %xmm0
-;   pxor    %xmm6, %xmm6, %xmm6
-;   pshufb  %xmm0, %xmm6, %xmm0
+;   pxor    %xmm7, %xmm7, %xmm7
+;   pshufb  %xmm0, %xmm7, %xmm0
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -90,11 +90,11 @@ block0:
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   movl    $65535, %eax
-;   uninit  %xmm0
-;   pinsrw  $0, %xmm0, %rax, %xmm0
-;   pinsrw  $1, %xmm0, %rax, %xmm0
-;   pshufd  $0, %xmm0, %xmm0
+;   movl    $65535, %edi
+;   uninit  %xmm5
+;   pinsrw  $0, %xmm5, %rdi, %xmm5
+;   pinsrw  $1, %xmm5, %rdi, %xmm5
+;   pshufd  $0, %xmm5, %xmm0
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -108,9 +108,9 @@ block0(v0: i32):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   uninit  %xmm0
-;   pinsrd  $0, %xmm0, %rdi, %xmm0
-;   pshufd  $0, %xmm0, %xmm0
+;   uninit  %xmm4
+;   pinsrd  $0, %xmm4, %rdi, %xmm4
+;   pshufd  $0, %xmm4, %xmm0
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret
@@ -124,11 +124,11 @@ block0(v0: f64):
 ;   pushq   %rbp
 ;   movq    %rsp, %rbp
 ; block0:
-;   movdqa  %xmm0, %xmm4
+;   movdqa  %xmm0, %xmm6
 ;   uninit  %xmm0
-;   movdqa  %xmm4, %xmm5
-;   movsd   %xmm0, %xmm5, %xmm0
-;   movlhps %xmm0, %xmm5, %xmm0
+;   movdqa  %xmm6, %xmm7
+;   movsd   %xmm0, %xmm7, %xmm0
+;   movlhps %xmm0, %xmm7, %xmm0
 ;   movq    %rbp, %rsp
 ;   popq    %rbp
 ;   ret