diff --git a/lib/cretonne/meta/gen_encoding.py b/lib/cretonne/meta/gen_encoding.py
index 30d1ed3370..3d4a00c4cc 100644
--- a/lib/cretonne/meta/gen_encoding.py
+++ b/lib/cretonne/meta/gen_encoding.py
@@ -75,7 +75,7 @@ def emit_instp(instp, fmt):
     """
     iform = instp.predicate_context()
 
-    # Which fiels do we need in the InstructionData pattern match?
+    # Which fields do we need in the InstructionData pattern match?
     if iform.boxed_storage:
         fields = 'ref data'
     else:
@@ -99,10 +99,18 @@ def emit_instps(instps, fmt):
     """
 
     if not instps:
-        fmt.line('#[allow(unused_variables)]')
+        # If the ISA has no predicates, just emit a stub.
+        with fmt.indented(
+                'pub fn check_instp(_: &InstructionData, _: u16) ' +
+                '-> bool {', '}'):
+            fmt.line('unimplemented!()')
+        return
+
     with fmt.indented(
             'pub fn check_instp(inst: &InstructionData, instp_idx: u16) ' +
             '-> bool {', '}'):
+        # The matches emitted by `emit_instp` need this.
+        fmt.line('use ir::instructions::InstructionFormat;')
         with fmt.indented('match instp_idx {', '}'):
             for instp in instps:
                 emit_instp(instp, fmt)
diff --git a/lib/cretonne/src/isa/arm32/enc_tables.rs b/lib/cretonne/src/isa/arm32/enc_tables.rs
index 3c3ffae695..c464d92f23 100644
--- a/lib/cretonne/src/isa/arm32/enc_tables.rs
+++ b/lib/cretonne/src/isa/arm32/enc_tables.rs
@@ -1,7 +1,6 @@
 //! Encoding tables for ARM32 ISA.
 
 use ir::InstructionData;
-use ir::instructions::InstructionFormat;
 use ir::types;
 use isa::enc_tables::{Level1Entry, Level2Entry};
 use isa::constraints::*;
diff --git a/lib/cretonne/src/isa/arm64/enc_tables.rs b/lib/cretonne/src/isa/arm64/enc_tables.rs
index 92b5ad58c3..064a00f2e2 100644
--- a/lib/cretonne/src/isa/arm64/enc_tables.rs
+++ b/lib/cretonne/src/isa/arm64/enc_tables.rs
@@ -1,7 +1,6 @@
 //! Encoding tables for ARM64 ISA.
 
 use ir::InstructionData;
-use ir::instructions::InstructionFormat;
 use ir::types;
 use isa::enc_tables::{Level1Entry, Level2Entry};
 use isa::constraints::*;
diff --git a/lib/cretonne/src/isa/intel/enc_tables.rs b/lib/cretonne/src/isa/intel/enc_tables.rs
index 0b01f481f2..a29394a3a9 100644
--- a/lib/cretonne/src/isa/intel/enc_tables.rs
+++ b/lib/cretonne/src/isa/intel/enc_tables.rs
@@ -1,7 +1,6 @@
 //! Encoding tables for Intel ISAs.
 
 use ir::InstructionData;
-use ir::instructions::InstructionFormat;
 use ir::types;
 use isa::enc_tables::{Level1Entry, Level2Entry};
 use isa::constraints::*;
diff --git a/lib/cretonne/src/isa/riscv/enc_tables.rs b/lib/cretonne/src/isa/riscv/enc_tables.rs
index 2538911a25..f02ccf80ba 100644
--- a/lib/cretonne/src/isa/riscv/enc_tables.rs
+++ b/lib/cretonne/src/isa/riscv/enc_tables.rs
@@ -1,7 +1,6 @@
 //! Encoding tables for RISC-V.
 
 use ir::{Opcode, InstructionData};
-use ir::instructions::InstructionFormat;
 use ir::types;
 use predicates;
 use isa::enc_tables::{Level1Entry, Level2Entry};