Merge pull request #3314 from dheaton-arm/implement-bitops

Implement bit operations for Cranelift interpreter

cranelift/filetests/filetests/runtests/bitrev.clif

@@ -0,0 +1,40 @@
+test interpret
+test run
+target aarch64
+target x86_64
+
+function %bitrev_i8(i8) -> i8 {
+block0(v0: i8):
+    v1 = bitrev v0
+    return v1
+}
+; run: %bitrev_i8(1) == -128
+; run: %bitrev_i8(64) == 2
+; run: %bitrev_i8(-1) == -1
+
+function %bitrev_i16(i16) -> i16 {
+block0(v0: i16):
+    v1 = bitrev v0
+    return v1
+}
+; run: %bitrev_i16(1) == -32768
+; run: %bitrev_i16(16384) == 2
+; run: %bitrev_i16(-1) == -1
+
+function %bitrev_i32(i32) -> i32 {
+block0(v0: i32):
+    v1 = bitrev v0
+    return v1
+}
+; run: %bitrev_i32(1) == -2147483648
+; run: %bitrev_i32(1073741824) == 2
+; run: %bitrev_i32(-1) == -1
+
+function %bitrev_i64(i64) -> i64 {
+block0(v0: i64):
+    v1 = bitrev v0
+    return v1
+}
+; run: %bitrev_i64(1) == -9223372036854775808
+; run: %bitrev_i64(4611686018427387904) == 2
+; run: %bitrev_i64(-1) == -1

cranelift/filetests/filetests/runtests/cls-aarch64.clif

@@ -0,0 +1,24 @@
+test interpret
+test run
+target aarch64
+; not implemented on `x86_64`
+
+function %cls_i32(i32) -> i32 {
+block0(v0: i32):
+    v1 = cls v0
+    return v1
+}
+; run: %cls_i32(1) == 30
+; run: %cls_i32(0x40000000) == 0
+; run: %cls_i32(-1) == 31
+; run: %cls_i32(0) == 31
+
+function %cls_i64(i64) -> i64 {
+block0(v0: i64):
+    v1 = cls v0
+    return v1
+}
+; run: %cls_i64(1) == 62
+; run: %cls_i64(0x4000000000000000) == 0
+; run: %cls_i64(-1) == 63
+; run: %cls_i64(0) == 63

cranelift/filetests/filetests/runtests/cls-interpret.clif

@@ -0,0 +1,23 @@
+test interpret
+; aarch64 yields cls_i8(1) == 30, which is incorrect
+
+function %cls_i8(i8) -> i8 {
+block0(v0: i8):
+    v1 = cls v0
+    return v1
+}
+; run: %cls_i8(1) == 6
+; run: %cls_i8(0x40) == 0
+; run: %cls_i8(-1) == 7
+; run: %cls_i8(0) == 7
+
+function %cls_i16(i16) -> i16 {
+block0(v0: i16):
+    v1 = cls v0
+    return v1
+}
+; run: %cls_i16(1) == 14
+; run: %cls_i16(0x4000) == 0
+; run: %cls_i16(-1) == 15
+; run: %cls_i16(0) == 15
+

cranelift/filetests/filetests/runtests/clz-interpret.clif

@@ -0,0 +1,19 @@
+test interpret
+
+function %clz_i8(i8) -> i8 {
+block0(v0: i8):
+    v1 = clz v0
+    return v1
+}
+; run: %clz_i8(1) == 7
+; run: %clz_i8(0x40) == 1
+; run: %clz_i8(-1) == 0
+
+function %clz_i16(i16) -> i16 {
+block0(v0: i16):
+    v1 = clz v0
+    return v1
+}
+; run: %clz_i16(1) == 15
+; run: %clz_i16(0x4000) == 1
+; run: %clz_i16(-1) == 0

cranelift/filetests/filetests/runtests/clz.clif

@@ -0,0 +1,22 @@
+test interpret
+test run
+target aarch64
+target x86_64
+
+function %clz_i32(i32) -> i32 {
+block0(v0: i32):
+    v1 = clz v0
+    return v1
+}
+; run: %clz_i32(1) == 31
+; run: %clz_i32(0x40000000) == 1
+; run: %clz_i32(-1) == 0
+
+function %clz_i64(i64) -> i64 {
+block0(v0: i64):
+    v1 = clz v0
+    return v1
+}
+; run: %clz_i64(1) == 63
+; run: %clz_i64(0x4000000000000000) == 1
+; run: %clz_i64(-1) == 0

cranelift/filetests/filetests/runtests/ctz-interpret.clif

@@ -0,0 +1,19 @@
+test interpret
+
+function %ctz_i8(i8) -> i8 {
+block0(v0: i8):
+    v1 = ctz v0
+    return v1
+}
+; run: %ctz_i8(1) == 0
+; run: %ctz_i8(0x40) == 6
+; run: %ctz_i8(-1) == 0
+
+function %ctz_i16(i16) -> i16 {
+block0(v0: i16):
+    v1 = ctz v0
+    return v1
+}
+; run: %ctz_i16(1) == 0
+; run: %ctz_i16(0x4000) == 14
+; run: %ctz_i16(-1) == 0

cranelift/filetests/filetests/runtests/ctz.clif

@@ -0,0 +1,22 @@
+test interpret
+test run
+target aarch64
+target x86_64
+
+function %ctz_i32(i32) -> i32 {
+block0(v0: i32):
+    v1 = ctz v0
+    return v1
+}
+; run: %ctz_i32(1) == 0
+; run: %ctz_i32(0x40000000) == 30
+; run: %ctz_i32(-1) == 0
+
+function %ctz_i64(i64) -> i64 {
+block0(v0: i64):
+    v1 = ctz v0
+    return v1
+}
+; run: %ctz_i64(1) == 0
+; run: %ctz_i64(0x4000000000000000) == 62
+; run: %ctz_i64(-1) == 0

cranelift/filetests/filetests/runtests/popcnt-aarch64.clif

@@ -0,0 +1,50 @@
+test interpret
+test run
+target aarch64
+
+function %popcnt_i8(i8) -> i8 {
+block0(v0: i8):
+    v1 = popcnt v0
+    return v1
+}
+; run: %popcnt_i8(1) == 1
+; run: %popcnt_i8(0x40) == 1
+; run: %popcnt_i8(-1) == 8
+; run: %popcnt_i8(0) == 0
+
+function %popcnt_i16(i16) -> i16 {
+block0(v0: i16):
+    v1 = popcnt v0
+    return v1
+}
+; run: %popcnt_i16(1) == 1
+; run: %popcnt_i16(0x4000) == 1
+; run: %popcnt_i16(-1) == 16
+; run: %popcnt_i16(0) == 0
+
+function %popcnt_i32(i32) -> i32 {
+block0(v0: i32):
+    v1 = popcnt v0
+    return v1
+}
+; run: %popcnt_i32(1) == 1
+; run: %popcnt_i32(0x40000000) == 1
+; run: %popcnt_i32(-1) == 32
+; run: %popcnt_i32(0) == 0
+
+function %popcnt_i64(i64) -> i64 {
+block0(v0: i64):
+    v1 = popcnt v0
+    return v1
+}
+; run: %popcnt_i64(1) == 1
+; run: %popcnt_i64(0x4000000000000000) == 1
+; run: %popcnt_i64(-1) == 64
+; run: %popcnt_i64(0) == 0
+
+function %popcnt_i8x16(i8x16) -> i8x16 {
+block0(v0: i8x16):
+    v1 = popcnt v0
+    return v1
+}
+; run: %popcnt_i8x16([1 1 1 1 0x40 0x40 0x40 0x40 0xff 0xff 0xff 0xff 0 0 0 0]) == [1 1 1 1 1 1 1 1 8 8 8 8 0 0 0 0]

cranelift/filetests/filetests/runtests/popcnt-interpret.clif

@@ -0,0 +1,24 @@
+test interpret
+; i16x8 vectors aren't currently supported by the `AArch64` backend.
+
+function %popcnt_i16x8(i16x8) -> i16x8 {
+block0(v0: i16x8):
+    v1 = popcnt v0
+    return v1
+}
+; run: %popcnt_i16x8([1 1 0x4000 0x4000 0xffff 0xffff 0 0]) == [1 1 1 1 16 16 0 0]
+
+function %popcnt_i32x4(i32x4) -> i32x4 {
+block0(v0: i32x4):
+    v1 = popcnt v0
+    return v1
+}
+; run: %popcnt_i32x4([1 0x40000000 0xFFFFFFFF 0]) == [1 1 32 0]
+
+function %popcnt_i64x2(i64x2) -> i64x2 {
+block0(v0: i64x2):
+    v1 = popcnt v0
+    return v1
+}
+; run: %popcnt_i64x2([1 0x4000000000000000]) == [1 1]
+; run: %popcnt_i64x2([0xffffffffffffffff 0]) == [64 0]