ISLE: port extend/reduce opcodes on x64. (#3849)
This commit is contained in:
Chris Fallin
@@ -71,25 +71,6 @@ fn matches_input<C: LowerCtx<I = Inst>>(
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})
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}
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/// Returns whether the given specified `input` is a result produced by an instruction with any of
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/// the opcodes specified in `ops`.
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fn matches_input_any<C: LowerCtx<I = Inst>>(
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ctx: &mut C,
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input: InsnInput,
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ops: &[Opcode],
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) -> Option<IRInst> {
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let inputs = ctx.get_input_as_source_or_const(input.insn, input.input);
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inputs.inst.and_then(|(src_inst, _)| {
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let data = ctx.data(src_inst);
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for &op in ops {
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if data.opcode() == op {
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return Some(src_inst);
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}
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}
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None
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})
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}
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/// Emits instruction(s) to generate the given 64-bit constant value into a newly-allocated
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/// temporary register, returning that register.
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fn generate_constant<C: LowerCtx<I = Inst>>(ctx: &mut C, ty: Type, c: u64) -> ValueRegs<Reg> {
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@@ -917,122 +898,12 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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| Opcode::Popcnt
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| Opcode::Bitrev
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| Opcode::IsNull
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| Opcode::IsInvalid => implemented_in_isle(ctx),
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Opcode::Uextend | Opcode::Sextend | Opcode::Breduce | Opcode::Bextend | Opcode::Ireduce => {
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let src_ty = ctx.input_ty(insn, 0);
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let dst_ty = ctx.output_ty(insn, 0);
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if src_ty == types::I128 {
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assert!(dst_ty.bits() <= 64);
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assert!(op == Opcode::Ireduce);
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let src = put_input_in_regs(ctx, inputs[0]);
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let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
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ctx.emit(Inst::gen_move(dst, src.regs()[0], types::I64));
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} else if dst_ty == types::I128 {
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assert!(src_ty.bits() <= 64);
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let src = put_input_in_reg(ctx, inputs[0]);
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let dst = get_output_reg(ctx, outputs[0]);
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assert!(op == Opcode::Uextend || op == Opcode::Sextend);
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// Extend to 64 bits first.
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let ext_mode = ExtMode::new(src_ty.bits(), /* dst bits = */ 64);
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if let Some(ext_mode) = ext_mode {
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if op == Opcode::Sextend {
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ctx.emit(Inst::movsx_rm_r(ext_mode, RegMem::reg(src), dst.regs()[0]));
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} else {
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ctx.emit(Inst::movzx_rm_r(ext_mode, RegMem::reg(src), dst.regs()[0]));
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}
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} else {
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ctx.emit(Inst::mov64_rm_r(RegMem::reg(src), dst.regs()[0]));
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}
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// Now generate the top 64 bits.
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if op == Opcode::Sextend {
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// Sign-extend: move dst[0] into dst[1] and arithmetic-shift right by 63 bits
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// to spread the sign bit across all bits.
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ctx.emit(Inst::gen_move(
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dst.regs()[1],
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dst.regs()[0].to_reg(),
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types::I64,
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));
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ctx.emit(Inst::shift_r(
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OperandSize::Size64,
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ShiftKind::ShiftRightArithmetic,
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Some(63),
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dst.regs()[1],
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));
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} else {
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// Zero-extend: just zero the top word.
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ctx.emit(Inst::alu_rmi_r(
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OperandSize::Size64,
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AluRmiROpcode::Xor,
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RegMemImm::reg(dst.regs()[1].to_reg()),
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dst.regs()[1],
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));
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}
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} else {
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// Sextend requires a sign-extended move, but all the other opcodes are simply a move
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// from a zero-extended source. Here is why this works, in each case:
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//
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// - Breduce, Bextend: changing width of a boolean. We
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// represent a bool as a 0 or -1, so Breduce can mask, while
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// Bextend must sign-extend.
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//
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// - Ireduce: changing width of an integer. Smaller ints are stored with undefined
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// high-order bits, so we can simply do a copy.
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let is_sextend = match op {
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Opcode::Sextend | Opcode::Bextend => true,
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_ => false,
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};
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if src_ty == types::I32 && dst_ty == types::I64 && !is_sextend {
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// As a particular x64 extra-pattern matching opportunity, all the ALU opcodes on
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// 32-bits will zero-extend the upper 32-bits, so we can even not generate a
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// zero-extended move in this case.
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// TODO add loads and shifts here.
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if let Some(_) = matches_input_any(
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ctx,
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inputs[0],
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&[
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Opcode::Iadd,
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Opcode::IaddIfcout,
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Opcode::Isub,
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Opcode::Imul,
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Opcode::Band,
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Opcode::Bor,
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Opcode::Bxor,
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],
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) {
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let src = put_input_in_reg(ctx, inputs[0]);
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let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
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ctx.emit(Inst::gen_move(dst, src, types::I64));
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return Ok(());
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}
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}
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let src = input_to_reg_mem(ctx, inputs[0]);
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let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
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let ext_mode = ExtMode::new(src_ty.bits(), dst_ty.bits());
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assert_eq!(
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src_ty.bits() < dst_ty.bits(),
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ext_mode.is_some(),
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"unexpected extension: {} -> {}",
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src_ty,
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dst_ty
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);
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if let Some(ext_mode) = ext_mode {
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if is_sextend {
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ctx.emit(Inst::movsx_rm_r(ext_mode, src, dst));
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} else {
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ctx.emit(Inst::movzx_rm_r(ext_mode, src, dst));
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}
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} else {
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ctx.emit(Inst::mov64_rm_r(src, dst));
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}
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}
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}
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| Opcode::IsInvalid
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| Opcode::Uextend
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| Opcode::Sextend
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| Opcode::Breduce
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| Opcode::Bextend
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| Opcode::Ireduce => implemented_in_isle(ctx),
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Opcode::Bint => {
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// Booleans are stored as all-zeroes (0) or all-ones (-1). We AND
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