Add x86 SIMD band_not

cranelift/codegen/meta/src/isa/x86/encodings.rs

@@ -1982,6 +1982,10 @@ pub(crate) fn define<'defs>(
         let band = band.bind(vector(ty, sse_vector_size));
         e.enc_32_64(band, rec_fa.opcodes(&PAND));
 
+        // and not (note flipped recipe operands to match band_not order)
+        let band_not = band_not.bind(vector(ty, sse_vector_size));
+        e.enc_32_64(band_not, rec_fax.opcodes(&PANDN));
+
         // or
         let bor = bor.bind(vector(ty, sse_vector_size));
         e.enc_32_64(bor, rec_fa.opcodes(&POR));

cranelift/codegen/meta/src/isa/x86/opcodes.rs

@@ -266,6 +266,9 @@ pub static PADDUSW: [u8; 3] = [0x66, 0x0f, 0xdd];
 /// Bitwise AND of xmm2/m128 and xmm1 (SSE2).
 pub static PAND: [u8; 3] = [0x66, 0x0f, 0xdb];
 
+/// Bitwise AND NOT of xmm2/m128 and xmm1 (SSE2).
+pub static PANDN: [u8; 3] = [0x66, 0x0f, 0xdf];
+
 /// Compare packed data for equal (SSE2).
 pub static PCMPEQB: [u8; 3] = [0x66, 0x0f, 0x74];
 

cranelift/filetests/filetests/isa/x86/simd-logical-binemit.clif

@@ -19,3 +19,9 @@ ebb0(v0: b32x4 [%xmm4], v1: b32x4 [%xmm0]):
 [-, %xmm4]  v2 = bxor v0, v1      ; bin: 66 0f ef e0
             return v2
 }
+
+function %band_not_b64x2(b64x2, b64x2) -> b64x2 {
+ebb0(v0: b64x2 [%xmm6], v1: b64x2 [%xmm3]):
+[-, %xmm3]  v2 = band_not v0, v1      ; bin: 66 0f df de
+            return v2
+}

cranelift/filetests/filetests/isa/x86/simd-logical-run.clif

@@ -0,0 +1,23 @@
+test run
+set enable_simd
+target x86_64 skylake
+
+function %bnot() -> b32 {
+ebb0:
+    v0 = vconst.b32x4 [true true true false]
+    v1 = bnot v0
+    v2 = extractlane v1, 3
+    return v2
+}
+; run
+
+function %band_not() -> b1 {
+ebb0:
+    v0 = vconst.i16x8 [1 0 0 0 0 0 0 0]
+    v1 = vconst.i16x8 [0 0 0 0 0 0 0 0]
+    v2 = band_not v0, v1
+    v3 = extractlane v2, 0
+    v4 = icmp_imm eq v3, 1
+    return v4
+}
+; run