x64: fix AVX512 flag checks

Previously, the multiple flags for certain AVX512 instructions were
checked using `OR`: e.g., if the CPU has AVX512VL `OR` AVX512DQ,
emit `VPMULLQ`. This is incorrect--the logic should be `AND`. The Intel
Software Developer Manual, vol. 1, sec. 15.4, has more information on
this (notable there is the suggestion to check with `XGETBV` that the OS
is allowing the use of the XMM registers--but that is a separate issue).
This change switches to `AND` logic in the new backend.

cranelift/codegen/src/isa/x64/inst/emit.rs

@@ -137,7 +137,7 @@ pub(crate) fn emit(
     // Certain instructions may be present in more than one ISA feature set; we must at least match
     // one of them in the target CPU.
     let isa_requirements = inst.available_in_any_isa();
-    if !isa_requirements.is_empty() && !isa_requirements.iter().any(matches_isa_flags) {
+    if !isa_requirements.is_empty() && !isa_requirements.iter().all(matches_isa_flags) {
         panic!(
             "Cannot emit inst '{:?}' for target; failed to match ISA requirements: {:?}",
             inst, isa_requirements