Format with stable rustfmt-preview, then with rustfmt-0.9 again.

cranelift/src/compile.rs

@@ -7,7 +7,7 @@ use cretonne::settings::FlagsOrIsa;
 use cretonne::{binemit, ir};
 use cretonne::print_errors::pretty_error;
 use std::path::Path;
-use utils::{read_to_string, parse_sets_and_isa};
+use utils::{parse_sets_and_isa, read_to_string};
 
 struct PrintRelocs {
     flag_print: bool,

cranelift/src/cton-util.rs

@@ -1,15 +1,15 @@
 extern crate cretonne;
+extern crate cton_filetests;
 extern crate cton_reader;
 extern crate cton_wasm;
-extern crate cton_filetests;
 extern crate docopt;
+extern crate filecheck;
 #[macro_use]
 extern crate serde_derive;
-extern crate filecheck;
 extern crate tempdir;
 extern crate term;
 
-use cretonne::{VERSION, timing};
+use cretonne::{timing, VERSION};
 use docopt::Docopt;
 use std::io::{self, Write};
 use std::process;

cranelift/src/rsfilecheck.rs

@@ -4,7 +4,7 @@
 
 use CommandResult;
 use utils::read_to_string;
-use filecheck::{CheckerBuilder, Checker, NO_VARIABLES};
+use filecheck::{Checker, CheckerBuilder, NO_VARIABLES};
 use std::io::{self, Read};
 
 pub fn run(files: &[String], verbose: bool) -> CommandResult {

lib/cretonne/build.rs

@@ -18,7 +18,6 @@
 // The build script expects to be run from the directory where this build.rs file lives. The
 // current directory is used to find the sources.
 
-
 use std::env;
 use std::process;
 

lib/cretonne/src/abi.rs

@@ -3,7 +3,7 @@
 //! This module provides functions and data structures that are useful for implementing the
 //! `TargetIsa::legalize_signature()` method.
 
-use ir::{ArgumentLoc, AbiParam, ArgumentExtension, Type};
+use ir::{AbiParam, ArgumentExtension, ArgumentLoc, Type};
 use std::cmp::Ordering;
 use std::vec::Vec;
 

lib/cretonne/src/bforest/map.rs

@@ -2,7 +2,7 @@
 
 use packed_option::PackedOption;
 use std::marker::PhantomData;
-use super::{INNER_SIZE, Comparator, Forest, NodePool, Node, NodeData, Path};
+use super::{Comparator, Forest, Node, NodeData, NodePool, Path, INNER_SIZE};
 
 /// Tag type defining forest types for a map.
 struct MapTypes<K, V, C>(PhantomData<(K, V, C)>);

lib/cretonne/src/bforest/mod.rs

@@ -22,8 +22,8 @@ mod path;
 mod pool;
 mod set;
 
-pub use self::map::{MapForest, Map, MapCursor, MapIter};
+pub use self::map::{Map, MapCursor, MapForest, MapIter};
-pub use self::set::{SetForest, Set, SetCursor, SetIter};
+pub use self::set::{Set, SetCursor, SetForest, SetIter};
 
 use self::node::NodeData;
 use self::path::Path;

lib/cretonne/src/bforest/node.rs

@@ -2,7 +2,7 @@
 
 use std::borrow::{Borrow, BorrowMut};
 use std::fmt;
-use super::{Forest, Node, INNER_SIZE, SetValue, slice_insert, slice_shift};
+use super::{slice_insert, slice_shift, Forest, Node, SetValue, INNER_SIZE};
 
 /// B+-tree node.
 ///

lib/cretonne/src/bforest/path.rs

@@ -2,7 +2,7 @@
 
 use std::borrow::Borrow;
 use std::marker::PhantomData;
-use super::{Forest, Node, NodeData, NodePool, MAX_PATH, Comparator, slice_insert, slice_shift};
+use super::{slice_insert, slice_shift, Comparator, Forest, Node, NodeData, NodePool, MAX_PATH};
 use super::node::Removed;
 
 #[cfg(test)]
@@ -414,7 +414,6 @@ impl<F: Forest> Path<F> {
         }
     }
 
-
     /// Given that the current leaf node is in an unhealthy (underflowed or even empty) status,
     /// balance it with sibling nodes.
     ///
@@ -529,7 +528,6 @@ impl<F: Forest> Path<F> {
             // current entry[level] was one off the end of the node, it will now point at a proper
             // entry.
             debug_assert!(usize::from(self.entry[level]) < pool[self.node[level]].entries());
-
         } else if usize::from(self.entry[level]) >= pool[self.node[level]].entries() {
             // There's no right sibling at this level, so the node can't be rebalanced.
             // Check if we are in an off-the-end position.
@@ -703,7 +701,7 @@ impl<F: Forest> fmt::Display for Path<F> {
 mod test {
     use std::cmp::Ordering;
     use super::*;
-    use super::super::{Forest, NodePool, NodeData};
+    use super::super::{Forest, NodeData, NodePool};
 
     struct TC();
 

lib/cretonne/src/bforest/set.rs

@@ -2,7 +2,7 @@
 
 use packed_option::PackedOption;
 use std::marker::PhantomData;
-use super::{INNER_SIZE, Comparator, Forest, NodePool, Node, NodeData, Path, SetValue};
+use super::{Comparator, Forest, Node, NodeData, NodePool, Path, SetValue, INNER_SIZE};
 
 /// Tag type defining forest types for a set.
 struct SetTypes<K, C>(PhantomData<(K, C)>);

lib/cretonne/src/binemit/memorysink.rs

@@ -14,8 +14,8 @@
 //! relocations to a `RelocSink` trait object. Relocations are less frequent than the
 //! `CodeSink::put*` methods, so the performance impact of the virtual callbacks is less severe.
 
-use ir::{ExternalName, JumpTable, TrapCode, SourceLoc};
+use ir::{ExternalName, JumpTable, SourceLoc, TrapCode};
-use super::{CodeSink, CodeOffset, Reloc, Addend};
+use super::{Addend, CodeOffset, CodeSink, Reloc};
 use std::ptr::write_unaligned;
 
 /// A `CodeSink` that writes binary machine code directly into memory.

lib/cretonne/src/binemit/mod.rs

@@ -10,7 +10,7 @@ pub use regalloc::RegDiversions;
 pub use self::relaxation::relax_branches;
 pub use self::memorysink::{MemoryCodeSink, RelocSink, TrapSink};
 
-use ir::{ExternalName, JumpTable, Function, Inst, TrapCode, SourceLoc};
+use ir::{ExternalName, Function, Inst, JumpTable, SourceLoc, TrapCode};
 use std::fmt;
 
 /// Offset in bytes from the beginning of the function.

lib/cretonne/src/binemit/relaxation.rs

@@ -30,7 +30,7 @@
 use binemit::CodeOffset;
 use cursor::{Cursor, FuncCursor};
 use ir::{Function, InstructionData, Opcode};
-use isa::{TargetIsa, EncInfo};
+use isa::{EncInfo, TargetIsa};
 use iterators::IteratorExtras;
 use result::CtonError;
 

lib/cretonne/src/bitset.rs

@@ -6,8 +6,8 @@
 //! If you would like to add support for larger bitsets in the future, you need to change the trait
 //! bound Into<u32> and the u32 in the implementation of `max_bits()`.
 use std::mem::size_of;
-use std::ops::{Shl, BitOr, Sub, Add};
+use std::ops::{Add, BitOr, Shl, Sub};
-use std::convert::{Into, From};
+use std::convert::{From, Into};
 
 /// A small bitset built on a single primitive integer type
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]

lib/cretonne/src/cfg_printer.rs

@@ -1,6 +1,6 @@
 //! The `CFGPrinter` utility.
 
-use std::fmt::{Result, Write, Display, Formatter};
+use std::fmt::{Display, Formatter, Result, Write};
 
 use flowgraph::ControlFlowGraph;
 use ir::Function;

lib/cretonne/src/constant_hash.rs

@@ -18,7 +18,6 @@ pub trait Table<K: Copy + Eq> {
     fn key(&self, idx: usize) -> Option<K>;
 }
 
-
 /// Look for `key` in `table`.
 ///
 /// The provided `hash` value must have been computed from `key` using the same hash function that

lib/cretonne/src/context.rs

@@ -9,7 +9,7 @@
 //! contexts concurrently. Typically, you would have one context per compilation thread and only a
 //! single ISA instance.
 
-use binemit::{CodeOffset, relax_branches, MemoryCodeSink, RelocSink, TrapSink};
+use binemit::{relax_branches, CodeOffset, MemoryCodeSink, RelocSink, TrapSink};
 use dominator_tree::DominatorTree;
 use flowgraph::ControlFlowGraph;
 use ir::Function;

lib/cretonne/src/cursor.rs

@@ -637,7 +637,6 @@ impl<'c, 'f> ir::InstInserterBase<'c> for &'c mut FuncCursor<'f> {
     }
 }
 
-
 /// Encoding cursor.
 ///
 /// An `EncCursor` can be used to insert instructions that are immediately assigned an encoding.

lib/cretonne/src/dce.rs

@@ -6,7 +6,7 @@
 use cursor::{Cursor, FuncCursor};
 use dominator_tree::DominatorTree;
 use entity::EntityRef;
-use ir::{Function, Inst, Opcode, DataFlowGraph};
+use ir::{DataFlowGraph, Function, Inst, Opcode};
 use ir::instructions::InstructionData;
 use timing;
 use std::vec::Vec;

lib/cretonne/src/divconst_magic_numbers.rs

@@ -220,8 +220,8 @@ pub fn magicS64(d: i64) -> MS64 {
 
 #[cfg(test)]
 mod tests {
-    use super::{magicU32, magicU64, magicS32, magicS64};
+    use super::{magicS32, magicS64, magicU32, magicU64};
-    use super::{MU32, MU64, MS32, MS64};
+    use super::{MS32, MS64, MU32, MU64};
 
     fn mkMU32(mulBy: u32, doAdd: bool, shiftBy: i32) -> MU32 {
         MU32 {

lib/cretonne/src/dominator_tree.rs

@@ -1,8 +1,8 @@
 //! A Dominator Tree represented as mappings of Ebbs to their immediate dominator.
 
 use entity::EntityMap;
-use flowgraph::{ControlFlowGraph, BasicBlock};
+use flowgraph::{BasicBlock, ControlFlowGraph};
-use ir::{Ebb, Inst, Value, Function, Layout, ProgramOrder, ExpandedProgramPoint};
+use ir::{Ebb, ExpandedProgramPoint, Function, Inst, Layout, ProgramOrder, Value};
 use ir::instructions::BranchInfo;
 use packed_option::PackedOption;
 use std::cmp;
@@ -144,12 +144,12 @@ impl DominatorTree {
     {
         let (mut ebb_b, mut inst_b) = match b.into() {
             ExpandedProgramPoint::Ebb(ebb) => (ebb, None),
-            ExpandedProgramPoint::Inst(inst) => {
+            ExpandedProgramPoint::Inst(inst) => (
-                (
+                layout.inst_ebb(inst).expect(
-                    layout.inst_ebb(inst).expect("Instruction not in layout."),
+                    "Instruction not in layout.",
-                    Some(inst),
+                ),
-                )
+                Some(inst),
-            }
+            ),
         };
         let rpo_a = self.nodes[a].rpo_number;
 
@@ -460,7 +460,6 @@ impl DominatorTree {
             rpo_number: new_ebb_rpo,
             idom: Some(split_jump_inst).into(),
         };
-
     }
 
     // Insert new_ebb just after ebb in the RPO. This function checks

lib/cretonne/src/entity/list.rs

@@ -480,7 +480,7 @@ impl<T: EntityRef> EntityList<T> {
 #[cfg(test)]
 mod tests {
     use super::*;
-    use super::{sclass_size, sclass_for_length};
+    use super::{sclass_for_length, sclass_size};
     use ir::Inst;
     use entity::EntityRef;
 

lib/cretonne/src/entity/map.rs

@@ -1,6 +1,6 @@
 //! Densely numbered entity references as mapping keys.
 
-use entity::{EntityRef, Keys, Iter, IterMut};
+use entity::{EntityRef, Iter, IterMut, Keys};
 use std::marker::PhantomData;
 use std::ops::{Index, IndexMut};
 use std::vec::Vec;

lib/cretonne/src/entity/mod.rs

@@ -43,7 +43,7 @@ pub use self::list::{EntityList, ListPool};
 pub use self::map::EntityMap;
 pub use self::primary::PrimaryMap;
 pub use self::set::EntitySet;
-pub use self::sparse::{SparseSet, SparseMap, SparseMapValue};
+pub use self::sparse::{SparseMap, SparseMapValue, SparseSet};
 
 /// A type wrapping a small integer index should implement `EntityRef` so it can be used as the key
 /// of an `EntityMap` or `SparseMap`.

lib/cretonne/src/entity/primary.rs

@@ -1,5 +1,5 @@
 //! Densely numbered entity references as mapping keys.
-use entity::{EntityRef, Keys, Iter, IterMut};
+use entity::{EntityRef, Iter, IterMut, Keys};
 use std::marker::PhantomData;
 use std::ops::{Index, IndexMut};
 use std::vec::Vec;

lib/cretonne/src/entity/sparse.rs

@@ -7,7 +7,7 @@
 //! > Briggs, Torczon, *An efficient representation for sparse sets*,
 //!   ACM Letters on Programming Languages and Systems, Volume 2, Issue 1-4, March-Dec. 1993.
 
-use entity::{EntityRef, EntityMap};
+use entity::{EntityMap, EntityRef};
 use std::mem;
 use std::slice;
 use std::u32;

lib/cretonne/src/flowgraph.rs

@@ -24,7 +24,7 @@
 //! and `(Ebb0, jmp Ebb2)` respectively.
 
 use bforest;
-use ir::{Function, Inst, Ebb};
+use ir::{Ebb, Function, Inst};
 use ir::instructions::BranchInfo;
 use entity::EntityMap;
 use std::mem;
@@ -203,7 +203,7 @@ pub type SuccIter<'a> = bforest::SetIter<'a, Ebb, ()>;
 mod tests {
     use super::*;
     use cursor::{Cursor, FuncCursor};
-    use ir::{Function, InstBuilder, types};
+    use ir::{types, Function, InstBuilder};
     use std::vec::Vec;
 
     #[test]

lib/cretonne/src/ir/builder.rs

@@ -5,8 +5,8 @@
 
 use ir;
 use ir::types;
-use ir::{InstructionData, DataFlowGraph};
+use ir::{DataFlowGraph, InstructionData};
-use ir::{Opcode, Type, Inst, Value};
+use ir::{Inst, Opcode, Type, Value};
 use isa;
 
 /// Base trait for instruction builders.
@@ -145,8 +145,9 @@ where
 }
 
 impl<'f, IIB, Array> InstBuilderBase<'f> for InsertReuseBuilder<'f, IIB, Array>
-    where IIB: InstInserterBase<'f>,
+where
-          Array: AsRef<[Option<Value>]>
+    IIB: InstInserterBase<'f>,
+    Array: AsRef<[Option<Value>]>,
 {
     fn data_flow_graph(&self) -> &DataFlowGraph {
         self.inserter.data_flow_graph()

lib/cretonne/src/ir/dfg.rs

@@ -1,13 +1,13 @@
 //! Data flow graph tracking Instructions, Values, and EBBs.
 
-use entity::{PrimaryMap, EntityMap};
+use entity::{EntityMap, PrimaryMap};
-use isa::{TargetIsa, Encoding, Legalize};
+use isa::{Encoding, Legalize, TargetIsa};
 use ir;
 use ir::builder::ReplaceBuilder;
 use ir::extfunc::ExtFuncData;
-use ir::instructions::{InstructionData, CallInfo, BranchInfo};
+use ir::instructions::{BranchInfo, CallInfo, InstructionData};
 use ir::types;
-use ir::{Ebb, Inst, Value, Type, SigRef, Signature, FuncRef, ValueList, ValueListPool};
+use ir::{Ebb, FuncRef, Inst, SigRef, Signature, Type, Value, ValueList, ValueListPool};
 use packed_option::ReservedValue;
 use write::write_operands;
 use std::fmt;
@@ -775,7 +775,6 @@ impl DataFlowGraph {
         }
     }
 
-
     /// Append an existing value to `ebb`'s parameters.
     ///
     /// The appended value can't already be attached to something else.
@@ -863,7 +862,6 @@ impl<'a> fmt::Display for DisplayInst<'a> {
             write!(f, " = ")?;
         }
 
-
         let typevar = dfg.ctrl_typevar(inst);
         if typevar.is_void() {
             write!(f, "{}", dfg[inst].opcode())?;
@@ -1005,7 +1003,7 @@ mod tests {
     use super::*;
     use cursor::{Cursor, FuncCursor};
     use ir::types;
-    use ir::{Function, Opcode, InstructionData, TrapCode};
+    use ir::{Function, InstructionData, Opcode, TrapCode};
     use std::string::ToString;
 
     #[test]

lib/cretonne/src/ir/extfunc.rs

@@ -5,7 +5,7 @@
 //!
 //! This module declares the data types used to represent external functions and call signatures.
 
-use ir::{Type, ExternalName, SigRef, ArgumentLoc};
+use ir::{ArgumentLoc, ExternalName, SigRef, Type};
 use isa::{RegInfo, RegUnit};
 use std::cmp;
 use std::fmt;
@@ -379,7 +379,7 @@ impl FromStr for CallConv {
 #[cfg(test)]
 mod tests {
     use super::*;
-    use ir::types::{I32, F32, B8};
+    use ir::types::{B8, F32, I32};
     use std::string::ToString;
 
     #[test]

lib/cretonne/src/ir/function.rs

@@ -4,13 +4,13 @@
 //! instructions.
 
 use binemit::CodeOffset;
-use entity::{PrimaryMap, EntityMap};
+use entity::{EntityMap, PrimaryMap};
 use ir;
-use ir::{ExternalName, CallConv, Signature, DataFlowGraph, Layout};
+use ir::{CallConv, DataFlowGraph, ExternalName, Layout, Signature};
-use ir::{InstEncodings, ValueLocations, JumpTables, StackSlots, EbbOffsets, SourceLocs};
+use ir::{EbbOffsets, InstEncodings, JumpTables, SourceLocs, StackSlots, ValueLocations};
-use ir::{Ebb, JumpTableData, JumpTable, StackSlotData, StackSlot, SigRef, ExtFuncData, FuncRef,
+use ir::{Ebb, ExtFuncData, FuncRef, GlobalVar, GlobalVarData, Heap, HeapData, JumpTable,
-         GlobalVarData, GlobalVar, HeapData, Heap};
+         JumpTableData, SigRef, StackSlot, StackSlotData};
-use isa::{TargetIsa, EncInfo, Legalize};
+use isa::{EncInfo, Legalize, TargetIsa};
 use std::fmt;
 use write::write_function;
 

lib/cretonne/src/ir/immediates.rs

@@ -184,7 +184,6 @@ impl Display for Uimm32 {
         } else {
             write_hex(i64::from(self.0), f)
         }
-
     }
 }
 
@@ -249,7 +248,6 @@ impl Display for Offset32 {
         } else {
             write_hex(val, f)
         }
-
     }
 }
 
@@ -461,7 +459,6 @@ fn parse_float(s: &str, w: u8, t: u8) -> Result<u64, &'static str> {
                     None => return Err("Invalid character"),
                 }
             }
-
         }
     }
 

lib/cretonne/src/ir/instructions.rs

@@ -12,7 +12,7 @@ use std::ops::{Deref, DerefMut};
 use std::vec::Vec;
 
 use ir;
-use ir::{Value, Type, Ebb, JumpTable, SigRef, FuncRef};
+use ir::{Ebb, FuncRef, JumpTable, SigRef, Type, Value};
 use ir::types;
 use isa;
 
@@ -73,7 +73,7 @@ impl FromStr for Opcode {
 
     /// Parse an Opcode name from a string.
     fn from_str(s: &str) -> Result<Opcode, &'static str> {
-        use constant_hash::{Table, simple_hash, probe};
+        use constant_hash::{probe, simple_hash, Table};
 
         impl<'a> Table<&'a str> for [Option<Opcode>] {
             fn len(&self) -> usize {
@@ -512,16 +512,12 @@ impl OperandConstraint {
             LaneOf => Bound(ctrl_type.lane_type()),
             AsBool => Bound(ctrl_type.as_bool()),
             HalfWidth => Bound(ctrl_type.half_width().expect("invalid type for half_width")),
-            DoubleWidth => {
+            DoubleWidth => Bound(ctrl_type.double_width().expect(
-                Bound(ctrl_type.double_width().expect(
+                "invalid type for double_width",
-                    "invalid type for double_width",
+            )),
-                ))
+            HalfVector => Bound(ctrl_type.half_vector().expect(
-            }
+                "invalid type for half_vector",
-            HalfVector => {
+            )),
-                Bound(ctrl_type.half_vector().expect(
-                    "invalid type for half_vector",
-                ))
-            }
             DoubleVector => Bound(ctrl_type.by(2).expect("invalid type for double_vector")),
         }
     }

lib/cretonne/src/ir/layout.rs

@@ -5,10 +5,10 @@
 
 use entity::EntityMap;
 use ir::{Ebb, Inst};
-use ir::progpoint::{ProgramOrder, ExpandedProgramPoint};
+use ir::progpoint::{ExpandedProgramPoint, ProgramOrder};
 use packed_option::PackedOption;
 use std::cmp;
-use std::iter::{Iterator, IntoIterator};
+use std::iter::{IntoIterator, Iterator};
 use timing;
 
 /// The `Layout` struct determines the layout of EBBs and instructions in a function. It does not
@@ -734,7 +734,6 @@ impl<'f> DoubleEndedIterator for Insts<'f> {
     }
 }
 
-
 #[cfg(test)]
 mod tests {
     use cursor::{Cursor, CursorPosition};

lib/cretonne/src/ir/mod.rs

@@ -22,29 +22,29 @@ mod sourceloc;
 mod trapcode;
 mod valueloc;
 
-pub use ir::builder::{InstBuilder, InstBuilderBase, InstInserterBase, InsertBuilder};
+pub use ir::builder::{InsertBuilder, InstBuilder, InstBuilderBase, InstInserterBase};
 pub use ir::dfg::{DataFlowGraph, ValueDef};
-pub use ir::entities::{Ebb, Inst, Value, StackSlot, GlobalVar, JumpTable, FuncRef, SigRef, Heap};
+pub use ir::entities::{Ebb, FuncRef, GlobalVar, Heap, Inst, JumpTable, SigRef, StackSlot, Value};
-pub use ir::extfunc::{Signature, CallConv, AbiParam, ArgumentExtension, ArgumentPurpose,
+pub use ir::extfunc::{AbiParam, ArgumentExtension, ArgumentPurpose, CallConv, ExtFuncData,
-                      ExtFuncData};
+                      Signature};
 pub use ir::extname::ExternalName;
 pub use ir::function::Function;
 pub use ir::globalvar::GlobalVarData;
-pub use ir::heap::{HeapData, HeapStyle, HeapBase};
+pub use ir::heap::{HeapBase, HeapData, HeapStyle};
-pub use ir::instructions::{Opcode, InstructionData, VariableArgs, ValueList, ValueListPool};
+pub use ir::instructions::{InstructionData, Opcode, ValueList, ValueListPool, VariableArgs};
 pub use ir::jumptable::JumpTableData;
 pub use ir::layout::Layout;
 pub use ir::libcall::LibCall;
 pub use ir::memflags::MemFlags;
-pub use ir::progpoint::{ProgramPoint, ProgramOrder, ExpandedProgramPoint};
+pub use ir::progpoint::{ExpandedProgramPoint, ProgramOrder, ProgramPoint};
 pub use ir::sourceloc::SourceLoc;
-pub use ir::stackslot::{StackSlots, StackSlotKind, StackSlotData};
+pub use ir::stackslot::{StackSlotData, StackSlotKind, StackSlots};
 pub use ir::trapcode::TrapCode;
 pub use ir::types::Type;
-pub use ir::valueloc::{ValueLoc, ArgumentLoc};
+pub use ir::valueloc::{ArgumentLoc, ValueLoc};
 
 use binemit;
-use entity::{PrimaryMap, EntityMap};
+use entity::{EntityMap, PrimaryMap};
 use isa;
 
 /// Map of value locations.

lib/cretonne/src/ir/progpoint.rs

@@ -147,7 +147,7 @@ pub trait ProgramOrder {
 mod tests {
     use super::*;
     use entity::EntityRef;
-    use ir::{Inst, Ebb};
+    use ir::{Ebb, Inst};
     use std::string::ToString;
 
     #[test]

lib/cretonne/src/ir/stackslot.rs

@@ -3,8 +3,8 @@
 //! The `StackSlotData` struct keeps track of a single stack slot in a function.
 //!
 
-use entity::{PrimaryMap, Keys, Iter, IterMut};
+use entity::{Iter, IterMut, Keys, PrimaryMap};
-use ir::{Type, StackSlot};
+use ir::{StackSlot, Type};
 use packed_option::PackedOption;
 use std::cmp;
 use std::fmt;

lib/cretonne/src/ir/types.rs

@@ -1,7 +1,7 @@
 //! Common types for the Cretonne code generator.
 
 use std::default::Default;
-use std::fmt::{self, Display, Debug, Formatter};
+use std::fmt::{self, Debug, Display, Formatter};
 
 /// The type of an SSA value.
 ///

lib/cretonne/src/isa/arm32/abi.rs

@@ -4,7 +4,7 @@ use ir;
 use isa::RegClass;
 use regalloc::AllocatableSet;
 use settings as shared_settings;
-use super::registers::{S, D, Q, GPR};
+use super::registers::{D, GPR, Q, S};
 
 /// Legalize `sig`.
 pub fn legalize_signature(

lib/cretonne/src/isa/arm32/binemit.rs

@@ -1,6 +1,6 @@
 //! Emitting binary ARM32 machine code.
 
-use binemit::{CodeSink, bad_encoding};
+use binemit::{bad_encoding, CodeSink};
 use ir::{Function, Inst};
 use regalloc::RegDiversions;
 

lib/cretonne/src/isa/arm32/mod.rs

@@ -6,11 +6,11 @@ mod binemit;
 mod enc_tables;
 mod registers;
 
-use binemit::{CodeSink, MemoryCodeSink, emit_function};
+use binemit::{emit_function, CodeSink, MemoryCodeSink};
 use super::super::settings as shared_settings;
 use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
 use isa::Builder as IsaBuilder;
-use isa::{TargetIsa, RegInfo, RegClass, EncInfo};
+use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
 use ir;
 use regalloc;
 use std::fmt;

lib/cretonne/src/isa/arm32/registers.rs

@@ -6,7 +6,7 @@ include!(concat!(env!("OUT_DIR"), "/registers-arm32.rs"));
 
 #[cfg(test)]
 mod tests {
-    use super::{INFO, GPR, S, D};
+    use super::{D, GPR, INFO, S};
     use isa::RegUnit;
     use std::string::{String, ToString};
 

lib/cretonne/src/isa/arm64/abi.rs

@@ -4,7 +4,7 @@ use ir;
 use isa::RegClass;
 use regalloc::AllocatableSet;
 use settings as shared_settings;
-use super::registers::{GPR, FPR};
+use super::registers::{FPR, GPR};
 
 /// Legalize `sig`.
 pub fn legalize_signature(

lib/cretonne/src/isa/arm64/binemit.rs

@@ -1,6 +1,6 @@
 //! Emitting binary ARM64 machine code.
 
-use binemit::{CodeSink, bad_encoding};
+use binemit::{bad_encoding, CodeSink};
 use ir::{Function, Inst};
 use regalloc::RegDiversions;
 

lib/cretonne/src/isa/arm64/mod.rs

@@ -6,11 +6,11 @@ mod binemit;
 mod enc_tables;
 mod registers;
 
-use binemit::{CodeSink, MemoryCodeSink, emit_function};
+use binemit::{emit_function, CodeSink, MemoryCodeSink};
 use super::super::settings as shared_settings;
 use isa::enc_tables::{lookup_enclist, Encodings};
 use isa::Builder as IsaBuilder;
-use isa::{TargetIsa, RegInfo, RegClass, EncInfo};
+use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
 use ir;
 use regalloc;
 use std::fmt;

lib/cretonne/src/isa/constraints.rs

@@ -9,7 +9,7 @@
 
 use binemit::CodeOffset;
 use isa::{RegClass, RegUnit};
-use ir::{Function, ValueLoc, Inst};
+use ir::{Function, Inst, ValueLoc};
 use regalloc::RegDiversions;
 
 /// Register constraint for a single value operand or instruction result.
@@ -205,6 +205,5 @@ mod tests {
         // Backward limit
         assert!(t1.contains(1000, 748));
         assert!(!t1.contains(1000, 746));
-
     }
 }

lib/cretonne/src/isa/enc_tables.rs

@@ -3,8 +3,8 @@
 //! This module contains types and functions for working with the encoding tables generated by
 //! `lib/cretonne/meta/gen_encoding.py`.
 
-use constant_hash::{Table, probe};
+use constant_hash::{probe, Table};
-use ir::{Type, Opcode, DataFlowGraph, InstructionData};
+use ir::{DataFlowGraph, InstructionData, Opcode, Type};
 use isa::{Encoding, Legalize};
 use settings::PredicateView;
 use std::ops::Range;

lib/cretonne/src/isa/encoding.rs

@@ -1,7 +1,7 @@
 //! The `Encoding` struct.
 
 use binemit::CodeOffset;
-use isa::constraints::{RecipeConstraints, BranchRange};
+use isa::constraints::{BranchRange, RecipeConstraints};
 use std::fmt;
 
 /// Bits needed to encode an instruction as binary machine code.

lib/cretonne/src/isa/intel/abi.rs

@@ -4,17 +4,16 @@ use ir;
 use isa::{RegClass, RegUnit, TargetIsa};
 use regalloc::AllocatableSet;
 use settings as shared_settings;
-use super::registers::{GPR, FPR, RU};
+use super::registers::{FPR, GPR, RU};
-use abi::{ArgAction, ValueConversion, ArgAssigner, legalize_args};
+use abi::{legalize_args, ArgAction, ArgAssigner, ValueConversion};
-use ir::{AbiParam, ArgumentPurpose, ArgumentLoc, ArgumentExtension, CallConv, InstBuilder};
+use ir::{AbiParam, ArgumentExtension, ArgumentLoc, ArgumentPurpose, CallConv, InstBuilder};
-use ir::stackslot::{StackSize, StackOffset};
+use ir::stackslot::{StackOffset, StackSize};
 use ir::immediates::Imm64;
 use stack_layout::layout_stack;
 use std::i32;
-use cursor::{Cursor, EncCursor, CursorPosition};
+use cursor::{Cursor, CursorPosition, EncCursor};
 use result;
 
-
 /// Argument registers for x86-64
 static ARG_GPRS: [RU; 6] = [RU::rdi, RU::rsi, RU::rdx, RU::rcx, RU::r8, RU::r9];
 

lib/cretonne/src/isa/intel/binemit.rs

@@ -1,9 +1,9 @@
 //! Emitting binary Intel machine code.
 
-use binemit::{CodeSink, Reloc, bad_encoding};
+use binemit::{bad_encoding, CodeSink, Reloc};
-use ir::{Function, Inst, Ebb, InstructionData, Opcode, TrapCode};
+use ir::{Ebb, Function, Inst, InstructionData, Opcode, TrapCode};
-use ir::condcodes::{CondCode, IntCC, FloatCC};
+use ir::condcodes::{CondCode, FloatCC, IntCC};
-use isa::{RegUnit, StackRef, StackBase, StackBaseMask};
+use isa::{RegUnit, StackBase, StackBaseMask, StackRef};
 use regalloc::RegDiversions;
 use super::registers::RU;
 

lib/cretonne/src/isa/intel/enc_tables.rs

@@ -22,7 +22,6 @@ fn expand_sdivrem(
     cfg: &mut ControlFlowGraph,
     isa: &isa::TargetIsa,
 ) {
-
     let (x, y, is_srem) = match func.dfg[inst] {
         ir::InstructionData::Binary {
             opcode: ir::Opcode::Sdiv,
@@ -113,7 +112,6 @@ fn expand_udivrem(
     _cfg: &mut ControlFlowGraph,
     isa: &isa::TargetIsa,
 ) {
-
     let (x, y, is_urem) = match func.dfg[inst] {
         ir::InstructionData::Binary {
             opcode: ir::Opcode::Udiv,
@@ -324,7 +322,7 @@ fn expand_fcvt_to_sint(
     cfg: &mut ControlFlowGraph,
     _isa: &isa::TargetIsa,
 ) {
-    use ir::condcodes::{IntCC, FloatCC};
+    use ir::condcodes::{FloatCC, IntCC};
     use ir::immediates::{Ieee32, Ieee64};
 
     let x;
@@ -423,7 +421,7 @@ fn expand_fcvt_to_uint(
     cfg: &mut ControlFlowGraph,
     _isa: &isa::TargetIsa,
 ) {
-    use ir::condcodes::{IntCC, FloatCC};
+    use ir::condcodes::{FloatCC, IntCC};
     use ir::immediates::{Ieee32, Ieee64};
 
     let x;

lib/cretonne/src/isa/intel/mod.rs

@@ -6,11 +6,11 @@ mod binemit;
 mod enc_tables;
 mod registers;
 
-use binemit::{CodeSink, MemoryCodeSink, emit_function};
+use binemit::{emit_function, CodeSink, MemoryCodeSink};
 use super::super::settings as shared_settings;
 use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
 use isa::Builder as IsaBuilder;
-use isa::{TargetIsa, RegInfo, RegClass, EncInfo};
+use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
 use ir;
 use regalloc;
 use result;

lib/cretonne/src/isa/mod.rs

@@ -40,9 +40,9 @@
 //! The configured target ISA trait object is a `Box<TargetIsa>` which can be used for multiple
 //! concurrent function compilations.
 
-pub use isa::constraints::{RecipeConstraints, OperandConstraint, ConstraintKind, BranchRange};
+pub use isa::constraints::{BranchRange, ConstraintKind, OperandConstraint, RecipeConstraints};
-pub use isa::encoding::{Encoding, EncInfo};
+pub use isa::encoding::{EncInfo, Encoding};
-pub use isa::registers::{RegInfo, RegUnit, RegClass, RegClassIndex, regs_overlap};
+pub use isa::registers::{regs_overlap, RegClass, RegClassIndex, RegInfo, RegUnit};
 pub use isa::stack::{StackBase, StackBaseMask, StackRef};
 
 use binemit;
@@ -249,7 +249,7 @@ pub trait TargetIsa: fmt::Display {
         let _tt = timing::prologue_epilogue();
         // This default implementation is unlikely to be good enough.
         use stack_layout::layout_stack;
-        use ir::stackslot::{StackSize, StackOffset};
+        use ir::stackslot::{StackOffset, StackSize};
 
         let word_size = if self.flags().is_64bit() { 8 } else { 4 };
 

lib/cretonne/src/isa/riscv/abi.rs

@@ -5,12 +5,12 @@
 //!
 //! This doesn't support the soft-float ABI at the moment.
 
-use abi::{ArgAction, ValueConversion, ArgAssigner, legalize_args};
+use abi::{legalize_args, ArgAction, ArgAssigner, ValueConversion};
-use ir::{self, Type, AbiParam, ArgumentLoc, ArgumentExtension, ArgumentPurpose};
+use ir::{self, AbiParam, ArgumentExtension, ArgumentLoc, ArgumentPurpose, Type};
 use isa::RegClass;
 use regalloc::AllocatableSet;
 use settings as shared_settings;
-use super::registers::{GPR, FPR};
+use super::registers::{FPR, GPR};
 use super::settings;
 use std::i32;
 

lib/cretonne/src/isa/riscv/binemit.rs

@@ -1,8 +1,8 @@
 //! Emitting binary RISC-V machine code.
 
-use binemit::{CodeSink, Reloc, bad_encoding};
+use binemit::{bad_encoding, CodeSink, Reloc};
 use ir::{Function, Inst, InstructionData};
-use isa::{RegUnit, StackRef, StackBaseMask};
+use isa::{RegUnit, StackBaseMask, StackRef};
 use predicates::is_signed_int;
 use regalloc::RegDiversions;
 use std::u32;

lib/cretonne/src/isa/riscv/mod.rs

@@ -7,10 +7,10 @@ mod enc_tables;
 mod registers;
 
 use super::super::settings as shared_settings;
-use binemit::{CodeSink, MemoryCodeSink, emit_function};
+use binemit::{emit_function, CodeSink, MemoryCodeSink};
 use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
 use isa::Builder as IsaBuilder;
-use isa::{TargetIsa, RegInfo, RegClass, EncInfo};
+use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
 use ir;
 use regalloc;
 use std::fmt;
@@ -116,7 +116,7 @@ mod tests {
     use settings::{self, Configurable};
     use isa;
     use ir::{DataFlowGraph, InstructionData, Opcode};
-    use ir::{types, immediates};
+    use ir::{immediates, types};
     use std::string::{String, ToString};
 
     fn encstr(isa: &isa::TargetIsa, enc: Result<isa::Encoding, isa::Legalize>) -> String {

lib/cretonne/src/isa/riscv/registers.rs

@@ -6,7 +6,7 @@ include!(concat!(env!("OUT_DIR"), "/registers-riscv.rs"));
 
 #[cfg(test)]
 mod tests {
-    use super::{INFO, GPR, FPR};
+    use super::{FPR, GPR, INFO};
     use isa::RegUnit;
     use std::string::{String, ToString};
 

lib/cretonne/src/isa/riscv/settings.rs

@@ -22,12 +22,12 @@ mod tests {
         assert_eq!(
             f.to_string(),
             "[riscv]\n\
-                    supports_m = false\n\
+             supports_m = false\n\
-                    supports_a = false\n\
+             supports_a = false\n\
-                    supports_f = false\n\
+             supports_f = false\n\
-                    supports_d = false\n\
+             supports_d = false\n\
-                    enable_m = true\n\
+             enable_m = true\n\
-                    enable_e = false\n"
+             enable_e = false\n"
         );
         // Predicates are not part of the Display output.
         assert_eq!(f.full_float(), false);

lib/cretonne/src/isa/stack.rs

@@ -4,7 +4,7 @@
 //! defined in this module expresses the low-level details of accessing a stack slot from an
 //! encoded instruction.
 
-use ir::stackslot::{StackSlots, StackOffset, StackSlotKind};
+use ir::stackslot::{StackOffset, StackSlotKind, StackSlots};
 use ir::StackSlot;
 
 /// A method for referencing a stack slot in the current stack frame.

lib/cretonne/src/legalizer/boundary.rs

@@ -20,8 +20,8 @@
 use abi::{legalize_abi_value, ValueConversion};
 use cursor::{Cursor, FuncCursor};
 use flowgraph::ControlFlowGraph;
-use ir::{Function, DataFlowGraph, Inst, InstBuilder, Ebb, Type, Value, Signature, SigRef,
+use ir::{AbiParam, ArgumentLoc, ArgumentPurpose, DataFlowGraph, Ebb, Function, Inst, InstBuilder,
-         AbiParam, ArgumentPurpose, ArgumentLoc, ValueLoc};
+         SigRef, Signature, Type, Value, ValueLoc};
 use ir::instructions::CallInfo;
 use isa::TargetIsa;
 use legalizer::split::{isplit, vsplit};

lib/cretonne/src/legalizer/mod.rs

@@ -235,7 +235,6 @@ fn expand_select(
     cfg.recompute_ebb(pos.func, old_ebb);
 }
 
-
 /// Expand illegal `f32const` and `f64const` instructions.
 fn expand_fconst(
     inst: ir::Inst,

lib/cretonne/src/legalizer/split.rs

@@ -66,7 +66,7 @@
 
 use cursor::{Cursor, CursorPosition, FuncCursor};
 use flowgraph::ControlFlowGraph;
-use ir::{self, Ebb, Inst, Value, Type, Opcode, ValueDef, InstructionData, InstBuilder};
+use ir::{self, Ebb, Inst, InstBuilder, InstructionData, Opcode, Type, Value, ValueDef};
 use std::iter;
 use std::vec::Vec;
 
@@ -229,7 +229,6 @@ fn split_value(
                 let hi = pos.func.dfg.append_ebb_param(ebb, split_type);
                 reuse = Some((lo, hi));
 
-
                 // Now the original value is dangling. Insert a concatenation instruction that can
                 // compute it from the two new parameters. This also serves as a record of what we
                 // did so a future call to this function doesn't have to redo the work.

lib/cretonne/src/lib.rs

@@ -1,12 +1,7 @@
 //! Cretonne code generation library.
 
-#![deny(missing_docs,
+#![deny(missing_docs, trivial_numeric_casts, unused_extern_crates)]
-        trivial_numeric_casts,
+#![cfg_attr(feature = "clippy", plugin(clippy(conf_file = "../../clippy.toml")))]
-        unused_extern_crates)]
-
-#![cfg_attr(feature="clippy",
-            plugin(clippy(conf_file="../../clippy.toml")))]
-
 #![cfg_attr(feature="cargo-clippy", allow(
 // Rustfmt 0.9.0 is at odds with this lint:
                 block_in_if_condition_stmt,

lib/cretonne/src/licm.rs

@@ -1,7 +1,7 @@
 //! A Loop Invariant Code Motion optimization pass
 
 use cursor::{Cursor, FuncCursor};
-use ir::{Function, Ebb, Inst, Value, Type, InstBuilder, Layout, Opcode, DataFlowGraph};
+use ir::{DataFlowGraph, Ebb, Function, Inst, InstBuilder, Layout, Opcode, Type, Value};
 use flowgraph::ControlFlowGraph;
 use std::collections::HashSet;
 use dominator_tree::DominatorTree;
@@ -121,7 +121,6 @@ fn has_pre_header(
     result
 }
 
-
 // Change the destination of a jump or branch instruction. Does nothing if called with a non-jump
 // or non-branch instruction.
 fn change_branch_jump_destination(inst: Inst, new_ebb: Ebb, func: &mut Function) {

lib/cretonne/src/loop_analysis.rs

@@ -2,10 +2,10 @@
 //! and parent in the loop tree.
 
 use dominator_tree::DominatorTree;
-use entity::{PrimaryMap, Keys};
+use entity::{Keys, PrimaryMap};
 use entity::EntityMap;
 use flowgraph::ControlFlowGraph;
-use ir::{Function, Ebb, Layout};
+use ir::{Ebb, Function, Layout};
 use packed_option::PackedOption;
 use timing;
 use std::vec::Vec;
@@ -218,7 +218,6 @@ impl LoopAnalysis {
                     }
                 }
             }
-
         }
     }
 }
@@ -227,7 +226,7 @@ impl LoopAnalysis {
 mod test {
 
     use cursor::{Cursor, FuncCursor};
-    use ir::{Function, InstBuilder, types};
+    use ir::{types, Function, InstBuilder};
     use loop_analysis::{Loop, LoopAnalysis};
     use flowgraph::ControlFlowGraph;
     use dominator_tree::DominatorTree;
@@ -257,7 +256,6 @@ mod test {
 
             cur.insert_ebb(ebb3);
             cur.ins().brnz(cond, ebb0, &[]);
-
         }
 
         let mut loop_analysis = LoopAnalysis::new();
@@ -317,7 +315,6 @@ mod test {
 
             cur.insert_ebb(ebb5);
             cur.ins().brnz(cond, ebb0, &[]);
-
         }
 
         let mut loop_analysis = LoopAnalysis::new();

lib/cretonne/src/postopt.rs

@@ -4,8 +4,8 @@
 
 use cursor::{Cursor, EncCursor};
 use ir::dfg::ValueDef;
-use ir::{Function, InstructionData, Value, InstBuilder, Ebb, Inst};
+use ir::{Ebb, Function, Inst, InstBuilder, InstructionData, Value};
-use ir::condcodes::{CondCode, IntCC, FloatCC};
+use ir::condcodes::{CondCode, FloatCC, IntCC};
 use ir::instructions::{Opcode, ValueList};
 use ir::immediates::Imm64;
 use isa::TargetIsa;
@@ -67,54 +67,48 @@ fn optimize_cpu_flags(
                         cond,
                         args: cmp_args,
                         ..
-                    } => {
+                    } => CmpBrInfo {
-                        CmpBrInfo {
+                        br_inst: inst,
-                            br_inst: inst,
+                        cmp_inst: cond_inst,
-                            cmp_inst: cond_inst,
+                        destination,
-                            destination,
+                        args: args.clone(),
-                            args: args.clone(),
+                        cmp_arg: cmp_args[0],
-                            cmp_arg: cmp_args[0],
+                        invert_branch_cond,
-                            invert_branch_cond,
+                        kind: CmpBrKind::Icmp {
-                            kind: CmpBrKind::Icmp {
+                            cond,
-                                cond,
+                            arg: cmp_args[1],
-                                arg: cmp_args[1],
+                        },
-                            },
+                    },
-                        }
-                    }
                     InstructionData::IntCompareImm {
                         cond,
                         arg: cmp_arg,
                         imm: cmp_imm,
                         ..
-                    } => {
+                    } => CmpBrInfo {
-                        CmpBrInfo {
+                        br_inst: inst,
-                            br_inst: inst,
+                        cmp_inst: cond_inst,
-                            cmp_inst: cond_inst,
+                        destination,
-                            destination,
+                        args: args.clone(),
-                            args: args.clone(),
+                        cmp_arg,
-                            cmp_arg,
+                        invert_branch_cond,
-                            invert_branch_cond,
+                        kind: CmpBrKind::IcmpImm { cond, imm: cmp_imm },
-                            kind: CmpBrKind::IcmpImm { cond, imm: cmp_imm },
+                    },
-                        }
-                    }
                     InstructionData::FloatCompare {
                         cond,
                         args: cmp_args,
                         ..
-                    } => {
+                    } => CmpBrInfo {
-                        CmpBrInfo {
+                        br_inst: inst,
-                            br_inst: inst,
+                        cmp_inst: cond_inst,
-                            cmp_inst: cond_inst,
+                        destination,
-                            destination,
+                        args: args.clone(),
-                            args: args.clone(),
+                        cmp_arg: cmp_args[0],
-                            cmp_arg: cmp_args[0],
+                        invert_branch_cond,
-                            invert_branch_cond,
+                        kind: CmpBrKind::Fcmp {
-                            kind: CmpBrKind::Fcmp {
+                            cond,
-                                cond,
+                            arg: cmp_args[1],
-                                arg: cmp_args[1],
+                        },
-                            },
+                    },
-                        }
-                    }
                     _ => return,
                 }
             } else {
@@ -179,7 +173,6 @@ fn optimize_cpu_flags(
     pos.func.update_encoding(info.br_inst, isa).is_ok();
 }
 
-
 //----------------------------------------------------------------------
 //
 // The main post-opt pass.
@@ -204,7 +197,6 @@ pub fn do_postopt(func: &mut Function, isa: &TargetIsa) {
                         last_flags_clobber = Some(inst)
                     }
                 }
-
             }
         }
     }

lib/cretonne/src/preopt.rs

@@ -4,15 +4,14 @@
 
 use cursor::{Cursor, FuncCursor};
 use ir::dfg::ValueDef;
-use ir::{Function, InstructionData, Value, DataFlowGraph, InstBuilder, Type};
+use ir::{DataFlowGraph, Function, InstBuilder, InstructionData, Type, Value};
 use ir::Inst;
 use ir::types::{I32, I64};
 use ir::instructions::Opcode;
-use divconst_magic_numbers::{MU32, MU64, MS32, MS64};
+use divconst_magic_numbers::{MS32, MS64, MU32, MU64};
-use divconst_magic_numbers::{magicU32, magicU64, magicS32, magicS64};
+use divconst_magic_numbers::{magicS32, magicS64, magicU32, magicU64};
 use timing;
 
-
 //----------------------------------------------------------------------
 //
 // Pattern-match helpers and transformation for div and rem by constants.
@@ -149,7 +148,6 @@ fn do_divrem_transformation(divrem_info: &DivRemByConstInfo, pos: &mut FuncCurso
     };
 
     match *divrem_info {
-
         // -------------------- U32 --------------------
 
         // U32 div, rem by zero: ignore
@@ -447,7 +445,6 @@ fn do_divrem_transformation(divrem_info: &DivRemByConstInfo, pos: &mut FuncCurso
                 }
             }
         }
-
     }
 }
 
@@ -554,13 +551,11 @@ fn simplify(pos: &mut FuncCursor, inst: Inst) {
     }
 }
 
-
 /// The main pre-opt pass.
 pub fn do_preopt(func: &mut Function) {
     let _tt = timing::preopt();
     let mut pos = FuncCursor::new(func);
     while let Some(_ebb) = pos.next_ebb() {
-
         while let Some(inst) = pos.next_inst() {
             // Apply basic simplifications.
             simplify(&mut pos, inst);

lib/cretonne/src/regalloc/affinity.rs

@@ -10,7 +10,7 @@
 
 use std::fmt;
 use ir::{AbiParam, ArgumentLoc};
-use isa::{TargetIsa, RegInfo, RegClassIndex, OperandConstraint, ConstraintKind};
+use isa::{ConstraintKind, OperandConstraint, RegClassIndex, RegInfo, TargetIsa};
 
 /// Preferred register allocation for an SSA value.
 #[derive(Clone, Copy, Debug)]

lib/cretonne/src/regalloc/allocatable_set.rs

@@ -5,7 +5,7 @@
 //! "register unit" abstraction. Every register contains one or more register units. Registers that
 //! share a register unit can't be in use at the same time.
 
-use isa::registers::{RegInfo, RegUnit, RegUnitMask, RegClass};
+use isa::registers::{RegClass, RegInfo, RegUnit, RegUnitMask};
 use std::char;
 use std::fmt;
 use std::iter::ExactSizeIterator;

lib/cretonne/src/regalloc/coalescing.rs

@@ -10,7 +10,7 @@ use dbg::DisplayList;
 use dominator_tree::{DominatorTree, DominatorTreePreorder};
 use flowgraph::ControlFlowGraph;
 use ir::{self, InstBuilder, ProgramOrder};
-use ir::{Function, Ebb, Inst, Value, ExpandedProgramPoint};
+use ir::{Ebb, ExpandedProgramPoint, Function, Inst, Value};
 use regalloc::affinity::Affinity;
 use regalloc::liveness::Liveness;
 use regalloc::virtregs::{VirtReg, VirtRegs};
@@ -19,7 +19,7 @@ use std::iter;
 use std::fmt;
 use std::slice;
 use std::vec::Vec;
-use isa::{TargetIsa, EncInfo};
+use isa::{EncInfo, TargetIsa};
 use timing;
 
 // # Implementation
@@ -92,7 +92,6 @@ impl Coalescing {
             predecessors: Vec::new(),
             backedges: Vec::new(),
         }
-
     }
 
     /// Clear all data structures in this coalescing pass.

lib/cretonne/src/regalloc/coloring.rs

@@ -44,10 +44,10 @@
 
 use cursor::{Cursor, EncCursor};
 use dominator_tree::DominatorTree;
-use ir::{Ebb, Inst, Value, Function, Layout, ValueLoc, SigRef};
+use ir::{Ebb, Function, Inst, Layout, SigRef, Value, ValueLoc};
-use ir::{InstBuilder, AbiParam, ArgumentLoc, ValueDef};
+use ir::{AbiParam, ArgumentLoc, InstBuilder, ValueDef};
-use isa::{RegUnit, RegClass, RegInfo, regs_overlap};
+use isa::{regs_overlap, RegClass, RegInfo, RegUnit};
-use isa::{TargetIsa, EncInfo, RecipeConstraints, OperandConstraint, ConstraintKind};
+use isa::{ConstraintKind, EncInfo, OperandConstraint, RecipeConstraints, TargetIsa};
 use packed_option::PackedOption;
 use regalloc::RegDiversions;
 use regalloc::affinity::Affinity;
@@ -59,7 +59,6 @@ use regalloc::solver::{Solver, SolverError};
 use std::mem;
 use timing;
 
-
 /// Data structures for the coloring pass.
 ///
 /// These are scratch space data structures that can be reused between invocations.
@@ -268,7 +267,6 @@ impl<'a> Context<'a> {
                             abi.display(&self.reginfo)
                         );
                     }
-
                 }
                 // The spiller will have assigned an incoming stack slot already.
                 Affinity::Stack => debug_assert!(abi.location.is_stack()),
@@ -426,7 +424,6 @@ impl<'a> Context<'a> {
             self.iterate_solution(throughs, &regs.global, &mut replace_global_defines)
         });
 
-
         // The solution and/or fixed input constraints may require us to shuffle the set of live
         // registers around.
         self.shuffle_inputs(&mut regs.input);
@@ -722,7 +719,6 @@ impl<'a> Context<'a> {
                 ConstraintKind::Reg |
                 ConstraintKind::Tied(_) |
                 ConstraintKind::Stack => {}
-
             }
         }
     }
@@ -869,7 +865,6 @@ impl<'a> Context<'a> {
                     self.solver.clear_all_global_flags();
                 }
             };
-
         }
     }
 

lib/cretonne/src/regalloc/context.rs

@@ -18,7 +18,7 @@ use regalloc::virtregs::VirtRegs;
 use result::CtonResult;
 use timing;
 use topo_order::TopoOrder;
-use verifier::{verify_context, verify_liveness, verify_cssa, verify_locations};
+use verifier::{verify_context, verify_cssa, verify_liveness, verify_locations};
 
 /// Persistent memory allocations for register allocation.
 pub struct Context {
@@ -106,7 +106,6 @@ impl Context {
             verify_cssa(func, cfg, domtree, &self.liveness, &self.virtregs)?;
         }
 
-
         // Pass: Spilling.
         self.spilling.run(
             isa,

lib/cretonne/src/regalloc/diversion.rs

@@ -7,9 +7,9 @@
 //! These register diversions are local to an EBB. No values can be diverted when entering a new
 //! EBB.
 
-use ir::{Value, ValueLoc, ValueLocations, StackSlot};
+use ir::{StackSlot, Value, ValueLoc, ValueLocations};
 use ir::{InstructionData, Opcode};
-use isa::{RegUnit, RegInfo};
+use isa::{RegInfo, RegUnit};
 use std::fmt;
 use std::vec::Vec;
 

lib/cretonne/src/regalloc/live_value_tracker.rs

@@ -6,7 +6,7 @@
 
 use dominator_tree::DominatorTree;
 use entity::{EntityList, ListPool};
-use ir::{Inst, Ebb, Value, DataFlowGraph, Layout, ExpandedProgramPoint};
+use ir::{DataFlowGraph, Ebb, ExpandedProgramPoint, Inst, Layout, Value};
 use partition_slice::partition_slice;
 use regalloc::affinity::Affinity;
 use regalloc::liveness::Liveness;

lib/cretonne/src/regalloc/liveness.rs

@@ -178,10 +178,10 @@
 use entity::SparseMap;
 use flowgraph::ControlFlowGraph;
 use ir::dfg::ValueDef;
-use ir::{Function, Value, Inst, Ebb, Layout, ProgramPoint};
+use ir::{Ebb, Function, Inst, Layout, ProgramPoint, Value};
-use isa::{TargetIsa, EncInfo};
+use isa::{EncInfo, TargetIsa};
 use regalloc::affinity::Affinity;
-use regalloc::liverange::{LiveRange, LiveRangeForest, LiveRangeContext};
+use regalloc::liverange::{LiveRange, LiveRangeContext, LiveRangeForest};
 use std::mem;
 use std::ops::Index;
 use std::vec::Vec;
@@ -378,7 +378,6 @@ impl Liveness {
         mem::replace(&mut lr.affinity, Affinity::Stack)
     }
 
-
     /// Compute the live ranges of all SSA values used in `func`.
     /// This clears out any existing analysis stored in this data structure.
     pub fn compute(&mut self, isa: &TargetIsa, func: &mut Function, cfg: &ControlFlowGraph) {

lib/cretonne/src/regalloc/liverange.rs

@@ -109,7 +109,7 @@
 
 use bforest;
 use entity::SparseMapValue;
-use ir::{Inst, Ebb, Value, Layout, ProgramPoint, ExpandedProgramPoint, ProgramOrder};
+use ir::{Ebb, ExpandedProgramPoint, Inst, Layout, ProgramOrder, ProgramPoint, Value};
 use regalloc::affinity::Affinity;
 use std::cmp::Ordering;
 
@@ -457,9 +457,9 @@ impl<PO: ProgramOrder> SparseMapValue<Value> for GenLiveRange<PO> {
 mod tests {
     use super::{GenLiveRange, LiveRangeContext};
     use bforest;
-    use ir::{Inst, Ebb, Value};
+    use ir::{Ebb, Inst, Value};
     use entity::EntityRef;
-    use ir::{ProgramOrder, ExpandedProgramPoint};
+    use ir::{ExpandedProgramPoint, ProgramOrder};
     use std::cmp::Ordering;
     use std::vec::Vec;
 
@@ -543,7 +543,6 @@ mod tests {
                 // Save for next round.
                 prev_end = Some(end);
             }
-
         }
     }
 

lib/cretonne/src/regalloc/pressure.rs

@@ -36,7 +36,7 @@
 // Remove once we're using the pressure tracker.
 #![allow(dead_code)]
 
-use isa::registers::{RegInfo, MAX_TRACKED_TOPRCS, RegClass, RegClassMask};
+use isa::registers::{RegClass, RegClassMask, RegInfo, MAX_TRACKED_TOPRCS};
 use regalloc::AllocatableSet;
 use std::cmp::min;
 use std::fmt;
@@ -135,7 +135,7 @@ impl Pressure {
     /// `can_take()` to check again.
     fn check_avail(&self, rc: RegClass) -> RegClassMask {
         let entry = match self.toprc.get(rc.toprc as usize) {
-            None => return 0,  // Not a pressure tracked bank.
+            None => return 0, // Not a pressure tracked bank.
             Some(e) => e,
         };
         let mask = 1 << rc.toprc;
@@ -269,7 +269,7 @@ impl fmt::Display for Pressure {
 #[cfg(test)]
 #[cfg(build_arm32)]
 mod tests {
-    use isa::{TargetIsa, RegClass};
+    use isa::{RegClass, TargetIsa};
     use regalloc::AllocatableSet;
     use std::borrow::Borrow;
     use super::Pressure;

lib/cretonne/src/regalloc/reload.rs

@@ -12,10 +12,10 @@
 use cursor::{Cursor, EncCursor};
 use dominator_tree::DominatorTree;
 use entity::{SparseMap, SparseMapValue};
-use ir::{Ebb, Inst, Value, Function};
+use ir::{Ebb, Function, Inst, Value};
-use ir::{InstBuilder, AbiParam, ArgumentLoc};
+use ir::{AbiParam, ArgumentLoc, InstBuilder};
 use isa::RegClass;
-use isa::{TargetIsa, Encoding, EncInfo, RecipeConstraints, ConstraintKind};
+use isa::{ConstraintKind, EncInfo, Encoding, RecipeConstraints, TargetIsa};
 use regalloc::affinity::Affinity;
 use regalloc::live_value_tracker::{LiveValue, LiveValueTracker};
 use regalloc::liveness::Liveness;

lib/cretonne/src/regalloc/solver.rs

@@ -350,7 +350,6 @@ impl Move {
         }
     }
 
-
     /// Get the value being moved.
     fn value(&self) -> Value {
         match *self {
@@ -1161,9 +1160,9 @@ impl fmt::Display for Solver {
 mod tests {
     use entity::EntityRef;
     use ir::Value;
-    use isa::{TargetIsa, RegClass, RegUnit, RegInfo};
+    use isa::{RegClass, RegInfo, RegUnit, TargetIsa};
     use regalloc::AllocatableSet;
-    use super::{Solver, Move};
+    use super::{Move, Solver};
     use std::boxed::Box;
 
     // Make an arm32 `TargetIsa`, if possible.
@@ -1396,7 +1395,7 @@ mod tests {
                 mov(v15, gpr, r5, r3),
                 mov(v14, gpr, r4, r5),
                 mov(v13, gpr, r1, r4),
-                fill(v10, gpr, 0, r1), // Finally complete cycle 1.
+                fill(v10, gpr, 0, r1) // Finally complete cycle 1.
             ]
         );
     }

lib/cretonne/src/regalloc/spilling.rs

@@ -17,9 +17,9 @@
 
 use cursor::{Cursor, EncCursor};
 use dominator_tree::DominatorTree;
-use ir::{InstBuilder, Function, Ebb, Inst, Value, ValueLoc, SigRef};
+use ir::{Ebb, Function, Inst, InstBuilder, SigRef, Value, ValueLoc};
-use isa::registers::{RegClassMask, RegClassIndex};
+use isa::registers::{RegClassIndex, RegClassMask};
-use isa::{TargetIsa, RegInfo, EncInfo, RecipeConstraints, ConstraintKind};
+use isa::{ConstraintKind, EncInfo, RecipeConstraints, RegInfo, TargetIsa};
 use regalloc::affinity::Affinity;
 use regalloc::live_value_tracker::{LiveValue, LiveValueTracker};
 use regalloc::liveness::Liveness;
@@ -359,12 +359,10 @@ impl<'a> Context<'a> {
             if abi.location.is_reg() {
                 let (rci, spilled) = match self.liveness[arg].affinity {
                     Affinity::Reg(rci) => (rci, false),
-                    Affinity::Stack => {
+                    Affinity::Stack => (
-                        (
+                        self.cur.isa.regclass_for_abi_type(abi.value_type).into(),
-                            self.cur.isa.regclass_for_abi_type(abi.value_type).into(),
+                        true,
-                            true,
+                    ),
-                        )
-                    }
                     Affinity::None => panic!("Missing affinity for {}", arg),
                 };
                 let mut reguse = RegUse::new(arg, fixed_args + idx, rci);

lib/cretonne/src/regalloc/virtregs.rs

@@ -14,9 +14,9 @@
 use dbg::DisplayList;
 use dominator_tree::DominatorTreePreorder;
 use entity::{EntityList, ListPool};
-use entity::{PrimaryMap, EntityMap, Keys};
+use entity::{EntityMap, Keys, PrimaryMap};
 use entity::EntityRef;
-use ir::{Value, Function};
+use ir::{Function, Value};
 use packed_option::PackedOption;
 use ref_slice::ref_slice;
 use std::cmp::Ordering;

lib/cretonne/src/scoped_hash_map.rs

@@ -4,7 +4,7 @@
 //! container that has a concept of scopes that can be entered and exited, such that
 //! values inserted while inside a scope aren't visible outside the scope.
 
-use std::collections::{HashMap, hash_map};
+use std::collections::{hash_map, HashMap};
 use std::hash::Hash;
 use std::mem;
 

lib/cretonne/src/settings.rs

@@ -357,18 +357,18 @@ mod tests {
         assert_eq!(
             f.to_string(),
             "[shared]\n\
-                    opt_level = \"default\"\n\
+             opt_level = \"default\"\n\
-                    enable_verifier = true\n\
+             enable_verifier = true\n\
-                    is_64bit = false\n\
+             is_64bit = false\n\
-                    is_pic = false\n\
+             is_pic = false\n\
-                    return_at_end = false\n\
+             return_at_end = false\n\
-                    avoid_div_traps = false\n\
+             avoid_div_traps = false\n\
-                    is_compressed = false\n\
+             is_compressed = false\n\
-                    enable_float = true\n\
+             enable_float = true\n\
-                    enable_simd = true\n\
+             enable_simd = true\n\
-                    enable_atomics = true\n\
+             enable_atomics = true\n\
-                    spiderwasm_prologue_words = 0\n\
+             spiderwasm_prologue_words = 0\n\
-                    allones_funcaddrs = false\n"
+             allones_funcaddrs = false\n"
         );
         assert_eq!(f.opt_level(), super::OptLevel::Default);
         assert_eq!(f.enable_simd(), true);

lib/cretonne/src/simple_gvn.rs

@@ -2,7 +2,7 @@
 
 use cursor::{Cursor, FuncCursor};
 use dominator_tree::DominatorTree;
-use ir::{InstructionData, Function, Inst, Opcode, Type};
+use ir::{Function, Inst, InstructionData, Opcode, Type};
 use scoped_hash_map::ScopedHashMap;
 use timing;
 use std::vec::Vec;

lib/cretonne/src/stack_layout.rs

@@ -1,9 +1,9 @@
 //! Computing stack layout.
 
 use ir::StackSlots;
-use ir::stackslot::{StackSize, StackOffset, StackSlotKind};
+use ir::stackslot::{StackOffset, StackSize, StackSlotKind};
 use result::CtonError;
-use std::cmp::{min, max};
+use std::cmp::{max, min};
 
 /// Compute the stack frame layout.
 ///
@@ -110,7 +110,7 @@ pub fn layout_stack(frame: &mut StackSlots, alignment: StackSize) -> Result<Stac
 
 #[cfg(test)]
 mod tests {
-    use ir::{StackSlots, StackSlotData, StackSlotKind};
+    use ir::{StackSlotData, StackSlotKind, StackSlots};
     use ir::types;
     use super::layout_stack;
     use ir::stackslot::StackOffset;

lib/cretonne/src/timing.rs

@@ -4,7 +4,7 @@
 
 use std::fmt;
 
-pub use self::details::{TimingToken, PassTimes, take_current, add_to_current};
+pub use self::details::{add_to_current, take_current, PassTimes, TimingToken};
 
 // Each pass that can be timed is predefined with the `define_passes!` macro. Each pass has a
 // snake_case name and a plain text description used when printing out the timing report.
@@ -90,18 +90,17 @@ impl fmt::Display for Pass {
     }
 }
 
-
 /// Implementation details.
 ///
 /// This whole module can be gated on a `cfg` feature to provide a dummy implementation for
 /// performance-sensitive builds or restricted environments. The dummy implementation must provide
 /// `TimingToken` and `PassTimings` types and a `take_current` function.
 mod details {
-    use super::{Pass, NUM_PASSES, DESCRIPTIONS};
+    use super::{Pass, DESCRIPTIONS, NUM_PASSES};
     use std::cell::{Cell, RefCell};
     use std::fmt;
     use std::mem;
-    use std::time::{Instant, Duration};
+    use std::time::{Duration, Instant};
 
     /// A timing token is responsible for timing the currently running pass. Timing starts when it
     /// is created and ends when it is dropped.

lib/cretonne/src/verifier/cssa.rs

@@ -3,7 +3,7 @@
 use dbg::DisplayList;
 use dominator_tree::{DominatorTree, DominatorTreePreorder};
 use flowgraph::ControlFlowGraph;
-use ir::{Function, ExpandedProgramPoint};
+use ir::{ExpandedProgramPoint, Function};
 use regalloc::liveness::Liveness;
 use regalloc::virtregs::VirtRegs;
 use timing;

lib/cretonne/src/verifier/flags.rs

@@ -7,7 +7,7 @@ use ir;
 use isa;
 use packed_option::PackedOption;
 use std::result;
-use verifier::{Result, Error};
+use verifier::{Error, Result};
 use timing;
 
 /// Verify that CPU flags are used correctly.

lib/cretonne/src/verifier/liveness.rs

@@ -1,7 +1,7 @@
 //! Liveness verifier.
 
 use flowgraph::ControlFlowGraph;
-use ir::{Function, Inst, Value, ProgramOrder, ProgramPoint, ExpandedProgramPoint};
+use ir::{ExpandedProgramPoint, Function, Inst, ProgramOrder, ProgramPoint, Value};
 use ir::entities::AnyEntity;
 use isa::TargetIsa;
 use regalloc::liveness::Liveness;

lib/cretonne/src/verifier/mod.rs

@@ -60,9 +60,9 @@ use dominator_tree::DominatorTree;
 use entity::SparseSet;
 use flowgraph::ControlFlowGraph;
 use ir::entities::AnyEntity;
-use ir::instructions::{InstructionFormat, BranchInfo, ResolvedConstraint, CallInfo};
+use ir::instructions::{BranchInfo, CallInfo, InstructionFormat, ResolvedConstraint};
-use ir::{types, Function, ValueDef, Ebb, Inst, SigRef, FuncRef, ValueList, JumpTable, StackSlot,
+use ir::{types, ArgumentLoc, Ebb, FuncRef, Function, GlobalVar, Inst, JumpTable, Opcode, SigRef,
-         StackSlotKind, GlobalVar, Value, Type, Opcode, ValueLoc, ArgumentLoc};
+         StackSlot, StackSlotKind, Type, Value, ValueDef, ValueList, ValueLoc};
 use ir;
 use isa::TargetIsa;
 use iterators::IteratorExtras;
@@ -195,7 +195,6 @@ impl<'a> Verifier<'a> {
     }
 
     fn ebb_integrity(&self, ebb: Ebb, inst: Inst) -> Result {
-
         let is_terminator = self.func.dfg[inst].opcode().is_terminator();
         let is_last_inst = self.func.layout.last_inst(ebb) == Some(inst);
 
@@ -1155,7 +1154,7 @@ impl<'a> Verifier<'a> {
 
 #[cfg(test)]
 mod tests {
-    use super::{Verifier, Error};
+    use super::{Error, Verifier};
     use ir::Function;
     use ir::instructions::{InstructionData, Opcode};
     use entity::EntityList;

lib/cretonne/src/write.rs

@@ -3,9 +3,9 @@
 //! The `write` module provides the `write_function` function which converts an IR `Function` to an
 //! equivalent textual form. This textual form can be read back by the `cretonne-reader` crate.
 
-use ir::{Function, DataFlowGraph, Ebb, Inst, Value, ValueDef, Type, SigRef};
+use ir::{DataFlowGraph, Ebb, Function, Inst, SigRef, Type, Value, ValueDef};
-use isa::{TargetIsa, RegInfo};
+use isa::{RegInfo, TargetIsa};
-use std::fmt::{self, Result, Error, Write};
+use std::fmt::{self, Error, Result, Write};
 use std::result;
 use packed_option::ReservedValue;
 use std::string::String;
@@ -146,7 +146,6 @@ pub fn write_ebb(w: &mut Write, func: &Function, isa: Option<&TargetIsa>, ebb: E
     Ok(())
 }
 
-
 //----------------------------------------------------------------------
 //
 // Instructions
@@ -452,7 +451,7 @@ impl<'a> fmt::Display for DisplayValues<'a> {
 
 #[cfg(test)]
 mod tests {
-    use ir::{Function, ExternalName, StackSlotData, StackSlotKind};
+    use ir::{ExternalName, Function, StackSlotData, StackSlotKind};
     use ir::types;
     use std::string::ToString;
 

lib/filetests/src/concurrent.rs

@@ -6,12 +6,12 @@
 use cretonne::timing;
 use std::panic::catch_unwind;
 use std::path::{Path, PathBuf};
-use std::sync::mpsc::{channel, Sender, Receiver};
+use std::sync::mpsc::{channel, Receiver, Sender};
 use std::sync::{Arc, Mutex};
 use std::thread;
 use std::time::Duration;
 use num_cpus;
-use {TestResult, runone};
+use {runone, TestResult};
 
 /// Request sent to worker threads contains jobid and path.
 struct Request(usize, PathBuf);

lib/filetests/src/runner.rs

@@ -8,7 +8,7 @@ use std::fmt::{self, Display};
 use std::ffi::OsStr;
 use std::path::{Path, PathBuf};
 use std::time;
-use {TestResult, runone};
+use {runone, TestResult};
 use concurrent::{ConcurrentRunner, Reply};
 
 /// Timeout in seconds when we're not making progress.
@@ -302,7 +302,6 @@ impl TestRunner {
         // Inter-quartile range.
         let iqr = q3 - q1;
 
-
         // Cut-off for what we consider a 'slow' test: 3 IQR from the 75% quartile.
         //
         // Q3 + 1.5 IQR are the data points that would be plotted as outliers outside a box plot,
@@ -319,7 +318,6 @@ impl TestRunner {
         {
             println!("slow: {}", t)
         }
-
     }
 
     /// Scan pushed directories for tests and run them.

lib/filetests/src/runone.rs

@@ -13,8 +13,8 @@ use cretonne::verify_function;
 use cretonne::print_errors::pretty_verifier_error;
 use cton_reader::parse_test;
 use cton_reader::IsaSpec;
-use {TestResult, new_subtest};
+use {new_subtest, TestResult};
-use subtest::{SubTest, Context, Result};
+use subtest::{Context, Result, SubTest};
 
 /// Read an entire file into a string.
 fn read_to_string<P: AsRef<Path>>(path: P) -> io::Result<String> {
@@ -82,7 +82,6 @@ pub fn run(path: &Path) -> TestResult {
         run_one_test(last_tuple, Cow::Owned(func), &mut context)?;
     }
 
-
     Ok(started.elapsed())
 }
 

lib/filetests/src/subtest.rs

@@ -5,8 +5,8 @@ use std::borrow::Cow;
 use cretonne::ir::Function;
 use cretonne::isa::TargetIsa;
 use cretonne::settings::{Flags, FlagsOrIsa};
-use cton_reader::{Details, Comment};
+use cton_reader::{Comment, Details};
-use filecheck::{CheckerBuilder, Checker, NO_VARIABLES};
+use filecheck::{Checker, CheckerBuilder, NO_VARIABLES};
 
 pub type Result<T> = result::Result<T, String>;
 

lib/filetests/src/test_binemit.rs

@@ -13,7 +13,7 @@ use cretonne::ir::entities::AnyEntity;
 use cretonne::binemit::RegDiversions;
 use cretonne::print_errors::pretty_error;
 use cton_reader::TestCommand;
-use subtest::{SubTest, Context, Result};
+use subtest::{Context, Result, SubTest};
 use match_directive::match_directive;
 
 struct TestBinEmit;
@@ -43,8 +43,6 @@ impl TextSink {
     }
 }
 
-
-
 impl binemit::CodeSink for TextSink {
     fn offset(&self) -> binemit::CodeOffset {
         self.offset
@@ -80,23 +78,11 @@ impl binemit::CodeSink for TextSink {
         name: &ir::ExternalName,
         addend: binemit::Addend,
     ) {
-        write!(
+        write!(self.text, "{}({}", reloc, name,).unwrap();
-            self.text,
-            "{}({}",
-            reloc,
-            name,
-        ).unwrap();
         if addend != 0 {
-            write!(
+            write!(self.text, "{:+}", addend,).unwrap();
-                self.text,
-                "{:+}",
-                addend,
-            ).unwrap();
         }
-        write!(
+        write!(self.text, ") ",).unwrap();
-            self.text,
-            ") ",
-        ).unwrap();
     }
 
     fn reloc_jt(&mut self, reloc: binemit::Reloc, jt: ir::JumpTable) {
@@ -278,10 +264,10 @@ impl SubTest for TestBinEmit {
                             ));
                         }
                         return Err(format!(
-                                "No matching encodings for {} in {}",
+                            "No matching encodings for {} in {}",
-                                func.dfg.display_inst(inst, isa),
+                            func.dfg.display_inst(inst, isa),
-                                DisplayList(&encodings),
+                            DisplayList(&encodings),
-                            ));
+                        ));
                     }
                     let have = sink.text.trim();
                     if have != want {

lib/filetests/src/test_cat.rs

@@ -3,7 +3,7 @@
 use std::borrow::Cow;
 use cretonne::ir::Function;
 use cton_reader::TestCommand;
-use subtest::{self, SubTest, Context, Result as STResult};
+use subtest::{self, Context, Result as STResult, SubTest};
 
 /// Object implementing the `test cat` sub-test.
 ///

lib/filetests/src/test_compile.rs

@@ -7,7 +7,7 @@ use cretonne::ir;
 use cretonne;
 use cretonne::print_errors::pretty_error;
 use cton_reader::TestCommand;
-use subtest::{SubTest, Context, Result, run_filecheck};
+use subtest::{run_filecheck, Context, Result, SubTest};
 use std::borrow::Cow;
 use std::fmt::Write;
 

lib/filetests/src/test_dce.rs

@@ -9,7 +9,7 @@ use cretonne::ir::Function;
 use cretonne;
 use cretonne::print_errors::pretty_error;
 use cton_reader::TestCommand;
-use subtest::{SubTest, Context, Result, run_filecheck};
+use subtest::{run_filecheck, Context, Result, SubTest};
 use std::borrow::Cow;
 use std::fmt::Write;
 

lib/filetests/src/test_domtree.rs

@@ -17,7 +17,7 @@ use cretonne::flowgraph::ControlFlowGraph;
 use cretonne::ir::Function;
 use cretonne::ir::entities::AnyEntity;
 use cton_reader::TestCommand;
-use subtest::{SubTest, Context, Result, run_filecheck};
+use subtest::{run_filecheck, Context, Result, SubTest};
 use std::borrow::{Borrow, Cow};
 use std::collections::HashMap;
 use std::fmt::{self, Write};
@@ -76,7 +76,7 @@ impl SubTest for TestDomtree {
                         Some(got_inst) if got_inst != inst => {
                             return Err(format!(
                                 "mismatching idoms for {}:\n\
-                                                want: {}, got: {}",
+                                 want: {}, got: {}",
                                 src_ebb,
                                 inst,
                                 got_inst
@@ -85,7 +85,7 @@ impl SubTest for TestDomtree {
                         None => {
                             return Err(format!(
                                 "mismatching idoms for {}:\n\
-                                                want: {}, got: unreachable",
+                                 want: {}, got: unreachable",
                                 src_ebb,
                                 inst
                             ));
@@ -105,7 +105,7 @@ impl SubTest for TestDomtree {
             if let Some(got_inst) = domtree.idom(ebb) {
                 return Err(format!(
                     "mismatching idoms for renumbered {}:\n\
-                                    want: unrechable, got: {}",
+                     want: unrechable, got: {}",
                     ebb,
                     got_inst
                 ));