T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Format with stable rustfmt-preview, then with rustfmt-0.9 again.

Browse Source
This commit is contained in:
Dan Gohman
2018-03-30 13:17:15 -07:00
parent d7c66a8ec1
commit 8d5fecd324
127 changed files with 381 additions and 479 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
lib/cretonne/src/regalloc/affinity.rs
View File

@@ -10,7 +10,7 @@
use std::fmt;
use ir::{AbiParam, ArgumentLoc};
use isa::{TargetIsa, RegInfo, RegClassIndex, OperandConstraint, ConstraintKind};
use isa::{ConstraintKind, OperandConstraint, RegClassIndex, RegInfo, TargetIsa};
/// Preferred register allocation for an SSA value.
#[derive(Clone, Copy, Debug)]

2
lib/cretonne/src/regalloc/allocatable_set.rs
View File

@@ -5,7 +5,7 @@
//! "register unit" abstraction. Every register contains one or more register units. Registers that
//! share a register unit can't be in use at the same time.
use isa::registers::{RegInfo, RegUnit, RegUnitMask, RegClass};
use isa::registers::{RegClass, RegInfo, RegUnit, RegUnitMask};
use std::char;
use std::fmt;
use std::iter::ExactSizeIterator;

5
lib/cretonne/src/regalloc/coalescing.rs
View File

@@ -10,7 +10,7 @@ use dbg::DisplayList;
use dominator_tree::{DominatorTree, DominatorTreePreorder};
use flowgraph::ControlFlowGraph;
use ir::{self, InstBuilder, ProgramOrder};
use ir::{Function, Ebb, Inst, Value, ExpandedProgramPoint};
use ir::{Ebb, ExpandedProgramPoint, Function, Inst, Value};
use regalloc::affinity::Affinity;
use regalloc::liveness::Liveness;
use regalloc::virtregs::{VirtReg, VirtRegs};
@@ -19,7 +19,7 @@ use std::iter;
use std::fmt;
use std::slice;
use std::vec::Vec;
use isa::{TargetIsa, EncInfo};
use isa::{EncInfo, TargetIsa};
use timing;
// # Implementation
@@ -92,7 +92,6 @@ impl Coalescing {
predecessors: Vec::new(),
backedges: Vec::new(),
}
}
/// Clear all data structures in this coalescing pass.

13
lib/cretonne/src/regalloc/coloring.rs
View File

@@ -44,10 +44,10 @@
use cursor::{Cursor, EncCursor};
use dominator_tree::DominatorTree;
use ir::{Ebb, Inst, Value, Function, Layout, ValueLoc, SigRef};
use ir::{InstBuilder, AbiParam, ArgumentLoc, ValueDef};
use isa::{RegUnit, RegClass, RegInfo, regs_overlap};
use isa::{TargetIsa, EncInfo, RecipeConstraints, OperandConstraint, ConstraintKind};
use ir::{Ebb, Function, Inst, Layout, SigRef, Value, ValueLoc};
use ir::{AbiParam, ArgumentLoc, InstBuilder, ValueDef};
use isa::{regs_overlap, RegClass, RegInfo, RegUnit};
use isa::{ConstraintKind, EncInfo, OperandConstraint, RecipeConstraints, TargetIsa};
use packed_option::PackedOption;
use regalloc::RegDiversions;
use regalloc::affinity::Affinity;
@@ -59,7 +59,6 @@ use regalloc::solver::{Solver, SolverError};
use std::mem;
use timing;
/// Data structures for the coloring pass.
///
/// These are scratch space data structures that can be reused between invocations.
@@ -268,7 +267,6 @@ impl<'a> Context<'a> {
abi.display(&self.reginfo)
);
}
}
// The spiller will have assigned an incoming stack slot already.
Affinity::Stack => debug_assert!(abi.location.is_stack()),
@@ -426,7 +424,6 @@ impl<'a> Context<'a> {
self.iterate_solution(throughs, &regs.global, &mut replace_global_defines)
});
// The solution and/or fixed input constraints may require us to shuffle the set of live
// registers around.
self.shuffle_inputs(&mut regs.input);
@@ -722,7 +719,6 @@ impl<'a> Context<'a> {
ConstraintKind::Reg |
ConstraintKind::Tied(_) |
ConstraintKind::Stack => {}
}
}
}
@@ -869,7 +865,6 @@ impl<'a> Context<'a> {
self.solver.clear_all_global_flags();
}
};
}
}

3
lib/cretonne/src/regalloc/context.rs
View File

@@ -18,7 +18,7 @@ use regalloc::virtregs::VirtRegs;
use result::CtonResult;
use timing;
use topo_order::TopoOrder;
use verifier::{verify_context, verify_liveness, verify_cssa, verify_locations};
use verifier::{verify_context, verify_cssa, verify_liveness, verify_locations};
/// Persistent memory allocations for register allocation.
pub struct Context {
@@ -106,7 +106,6 @@ impl Context {
verify_cssa(func, cfg, domtree, &self.liveness, &self.virtregs)?;
}
// Pass: Spilling.
self.spilling.run(
isa,

4
lib/cretonne/src/regalloc/diversion.rs
View File

@@ -7,9 +7,9 @@
//! These register diversions are local to an EBB. No values can be diverted when entering a new
//! EBB.
use ir::{Value, ValueLoc, ValueLocations, StackSlot};
use ir::{StackSlot, Value, ValueLoc, ValueLocations};
use ir::{InstructionData, Opcode};
use isa::{RegUnit, RegInfo};
use isa::{RegInfo, RegUnit};
use std::fmt;
use std::vec::Vec;

2
lib/cretonne/src/regalloc/live_value_tracker.rs
View File

@@ -6,7 +6,7 @@
use dominator_tree::DominatorTree;
use entity::{EntityList, ListPool};
use ir::{Inst, Ebb, Value, DataFlowGraph, Layout, ExpandedProgramPoint};
use ir::{DataFlowGraph, Ebb, ExpandedProgramPoint, Inst, Layout, Value};
use partition_slice::partition_slice;
use regalloc::affinity::Affinity;
use regalloc::liveness::Liveness;

7
lib/cretonne/src/regalloc/liveness.rs
View File

@@ -178,10 +178,10 @@
use entity::SparseMap;
use flowgraph::ControlFlowGraph;
use ir::dfg::ValueDef;
use ir::{Function, Value, Inst, Ebb, Layout, ProgramPoint};
use isa::{TargetIsa, EncInfo};
use ir::{Ebb, Function, Inst, Layout, ProgramPoint, Value};
use isa::{EncInfo, TargetIsa};
use regalloc::affinity::Affinity;
use regalloc::liverange::{LiveRange, LiveRangeForest, LiveRangeContext};
use regalloc::liverange::{LiveRange, LiveRangeContext, LiveRangeForest};
use std::mem;
use std::ops::Index;
use std::vec::Vec;
@@ -378,7 +378,6 @@ impl Liveness {
mem::replace(&mut lr.affinity, Affinity::Stack)
}
/// Compute the live ranges of all SSA values used in `func`.
/// This clears out any existing analysis stored in this data structure.
pub fn compute(&mut self, isa: &TargetIsa, func: &mut Function, cfg: &ControlFlowGraph) {

7
lib/cretonne/src/regalloc/liverange.rs
View File

@@ -109,7 +109,7 @@
use bforest;
use entity::SparseMapValue;
use ir::{Inst, Ebb, Value, Layout, ProgramPoint, ExpandedProgramPoint, ProgramOrder};
use ir::{Ebb, ExpandedProgramPoint, Inst, Layout, ProgramOrder, ProgramPoint, Value};
use regalloc::affinity::Affinity;
use std::cmp::Ordering;
@@ -457,9 +457,9 @@ impl<PO: ProgramOrder> SparseMapValue<Value> for GenLiveRange<PO> {
mod tests {
use super::{GenLiveRange, LiveRangeContext};
use bforest;
use ir::{Inst, Ebb, Value};
use ir::{Ebb, Inst, Value};
use entity::EntityRef;
use ir::{ProgramOrder, ExpandedProgramPoint};
use ir::{ExpandedProgramPoint, ProgramOrder};
use std::cmp::Ordering;
use std::vec::Vec;
@@ -543,7 +543,6 @@ mod tests {
// Save for next round.
prev_end = Some(end);
}
}
}

6
lib/cretonne/src/regalloc/pressure.rs
View File

@@ -36,7 +36,7 @@
// Remove once we're using the pressure tracker.
#![allow(dead_code)]
use isa::registers::{RegInfo, MAX_TRACKED_TOPRCS, RegClass, RegClassMask};
use isa::registers::{RegClass, RegClassMask, RegInfo, MAX_TRACKED_TOPRCS};
use regalloc::AllocatableSet;
use std::cmp::min;
use std::fmt;
@@ -135,7 +135,7 @@ impl Pressure {
/// `can_take()` to check again.
fn check_avail(&self, rc: RegClass) -> RegClassMask {
let entry = match self.toprc.get(rc.toprc as usize) {
None => return 0, // Not a pressure tracked bank.
None => return 0, // Not a pressure tracked bank.
Some(e) => e,
};
let mask = 1 << rc.toprc;
@@ -269,7 +269,7 @@ impl fmt::Display for Pressure {
#[cfg(test)]
#[cfg(build_arm32)]
mod tests {
use isa::{TargetIsa, RegClass};
use isa::{RegClass, TargetIsa};
use regalloc::AllocatableSet;
use std::borrow::Borrow;
use super::Pressure;

6
lib/cretonne/src/regalloc/reload.rs
View File

@@ -12,10 +12,10 @@
use cursor::{Cursor, EncCursor};
use dominator_tree::DominatorTree;
use entity::{SparseMap, SparseMapValue};
use ir::{Ebb, Inst, Value, Function};
use ir::{InstBuilder, AbiParam, ArgumentLoc};
use ir::{Ebb, Function, Inst, Value};
use ir::{AbiParam, ArgumentLoc, InstBuilder};
use isa::RegClass;
use isa::{TargetIsa, Encoding, EncInfo, RecipeConstraints, ConstraintKind};
use isa::{ConstraintKind, EncInfo, Encoding, RecipeConstraints, TargetIsa};
use regalloc::affinity::Affinity;
use regalloc::live_value_tracker::{LiveValue, LiveValueTracker};
use regalloc::liveness::Liveness;

7
lib/cretonne/src/regalloc/solver.rs
View File

@@ -350,7 +350,6 @@ impl Move {
}
}
/// Get the value being moved.
fn value(&self) -> Value {
match *self {
@@ -1161,9 +1160,9 @@ impl fmt::Display for Solver {
mod tests {
use entity::EntityRef;
use ir::Value;
use isa::{TargetIsa, RegClass, RegUnit, RegInfo};
use isa::{RegClass, RegInfo, RegUnit, TargetIsa};
use regalloc::AllocatableSet;
use super::{Solver, Move};
use super::{Move, Solver};
use std::boxed::Box;
// Make an arm32 `TargetIsa`, if possible.
@@ -1396,7 +1395,7 @@ mod tests {
mov(v15, gpr, r5, r3),
mov(v14, gpr, r4, r5),
mov(v13, gpr, r1, r4),
fill(v10, gpr, 0, r1), // Finally complete cycle 1.
fill(v10, gpr, 0, r1) // Finally complete cycle 1.
]
);
}

16
lib/cretonne/src/regalloc/spilling.rs
View File

@@ -17,9 +17,9 @@
use cursor::{Cursor, EncCursor};
use dominator_tree::DominatorTree;
use ir::{InstBuilder, Function, Ebb, Inst, Value, ValueLoc, SigRef};
use isa::registers::{RegClassMask, RegClassIndex};
use isa::{TargetIsa, RegInfo, EncInfo, RecipeConstraints, ConstraintKind};
use ir::{Ebb, Function, Inst, InstBuilder, SigRef, Value, ValueLoc};
use isa::registers::{RegClassIndex, RegClassMask};
use isa::{ConstraintKind, EncInfo, RecipeConstraints, RegInfo, TargetIsa};
use regalloc::affinity::Affinity;
use regalloc::live_value_tracker::{LiveValue, LiveValueTracker};
use regalloc::liveness::Liveness;
@@ -359,12 +359,10 @@ impl<'a> Context<'a> {
if abi.location.is_reg() {
let (rci, spilled) = match self.liveness[arg].affinity {
Affinity::Reg(rci) => (rci, false),
Affinity::Stack => {
(
self.cur.isa.regclass_for_abi_type(abi.value_type).into(),
true,
)
}
Affinity::Stack => (
self.cur.isa.regclass_for_abi_type(abi.value_type).into(),
true,
),
Affinity::None => panic!("Missing affinity for {}", arg),
};
let mut reguse = RegUse::new(arg, fixed_args + idx, rci);

4
lib/cretonne/src/regalloc/virtregs.rs
View File

@@ -14,9 +14,9 @@
use dbg::DisplayList;
use dominator_tree::DominatorTreePreorder;
use entity::{EntityList, ListPool};
use entity::{PrimaryMap, EntityMap, Keys};
use entity::{EntityMap, Keys, PrimaryMap};
use entity::EntityRef;
use ir::{Value, Function};
use ir::{Function, Value};
use packed_option::PackedOption;
use ref_slice::ref_slice;
use std::cmp::Ordering;