cranelift: Introduce a feature to enable trace logs (#4484)
* Don't use `log::trace` directly but a feature-enabled `trace` macro * Don't emit disassembly based on the log level
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@@ -24,6 +24,7 @@ use crate::ir::{
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};
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use crate::machinst::*;
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use crate::timing;
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use crate::trace;
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use crate::ValueLocRange;
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use regalloc2::{
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Edit, Function as RegallocFunction, InstOrEdit, InstRange, Operand, OperandKind, PReg, PRegSet,
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@@ -587,7 +588,7 @@ impl<I: VCodeInst> VCodeBuilder<I> {
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// Translate blockparam args via the vreg aliases table as well.
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for arg in &mut self.vcode.branch_block_args {
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let new_arg = Self::resolve_vreg_alias_impl(&self.vcode.vreg_aliases, *arg);
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log::trace!("operandcollector: block arg {:?} -> {:?}", arg, new_arg);
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trace!("operandcollector: block arg {:?} -> {:?}", arg, new_arg);
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*arg = new_arg;
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}
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}
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@@ -806,7 +807,7 @@ impl<I: VCodeInst> VCode<I> {
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}
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for block in final_order {
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log::trace!("emitting block {:?}", block);
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trace!("emitting block {:?}", block);
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let new_offset = I::align_basic_block(buffer.cur_offset());
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while new_offset > buffer.cur_offset() {
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// Pad with NOPs up to the aligned block offset.
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@@ -829,7 +830,7 @@ impl<I: VCodeInst> VCode<I> {
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// Is this the first block? Emit the prologue directly if so.
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if block == self.entry {
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log::trace!(" -> entry block");
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trace!(" -> entry block");
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buffer.start_srcloc(SourceLoc::default());
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state.pre_sourceloc(SourceLoc::default());
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for inst in &prologue_insts {
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