cranelift: Introduce a feature to enable trace logs (#4484)
* Don't use `log::trace` directly but a feature-enabled `trace` macro * Don't emit disassembly based on the log level
This commit is contained in:
@@ -20,7 +20,7 @@ use crate::machinst::{
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LoweredBlock, MachLabel, Reg, VCode, VCodeBuilder, VCodeConstant, VCodeConstantData,
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VCodeConstants, VCodeInst, ValueRegs, Writable,
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};
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use crate::CodegenResult;
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use crate::{trace, CodegenResult};
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use alloc::boxed::Box;
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use alloc::vec::Vec;
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use core::convert::TryInto;
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@@ -506,7 +506,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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if value_regs[param].is_invalid() {
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let regs = alloc_vregs(ty, &mut next_vreg, &mut vcode)?;
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value_regs[param] = regs;
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log::trace!("bb {} param {}: regs {:?}", bb, param, regs);
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trace!("bb {} param {}: regs {:?}", bb, param, regs);
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}
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}
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for inst in f.layout.block_insts(bb) {
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@@ -515,7 +515,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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if value_regs[result].is_invalid() {
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let regs = alloc_vregs(ty, &mut next_vreg, &mut vcode)?;
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value_regs[result] = regs;
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log::trace!(
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trace!(
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"bb {} inst {} ({:?}): result {} regs {:?}",
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bb,
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inst,
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@@ -543,7 +543,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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for ret in &vcode.abi().signature().returns.clone() {
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let regs = alloc_vregs(ret.value_type, &mut next_vreg, &mut vcode)?;
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retval_regs.push(regs);
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log::trace!("retval gets regs {:?}", regs);
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trace!("retval gets regs {:?}", regs);
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}
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// Compute instruction colors, find constant instructions, and find instructions with
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@@ -557,16 +557,16 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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for inst in f.layout.block_insts(bb) {
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let side_effect = has_lowering_side_effect(f, inst);
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log::trace!("bb {} inst {} has color {}", bb, inst, cur_color);
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trace!("bb {} inst {} has color {}", bb, inst, cur_color);
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if side_effect {
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side_effect_inst_entry_colors.insert(inst, InstColor::new(cur_color));
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log::trace!(" -> side-effecting; incrementing color for next inst");
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trace!(" -> side-effecting; incrementing color for next inst");
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cur_color += 1;
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}
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// Determine if this is a constant; if so, add to the table.
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if let Some(c) = is_constant_64bit(f, inst) {
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log::trace!(" -> constant: {}", c);
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trace!(" -> constant: {}", c);
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inst_constants.insert(inst, c);
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}
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}
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@@ -627,7 +627,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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// Push args for a given inst onto the DFS stack.
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let push_args_on_stack = |stack: &mut StackVec<'a>, value| {
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log::trace!(" -> pushing args for {} onto stack", value);
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trace!(" -> pushing args for {} onto stack", value);
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if let ValueDef::Result(src_inst, _) = f.dfg.value_def(value) {
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stack.push(f.dfg.inst_args(src_inst).iter());
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}
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@@ -640,7 +640,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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while let Some(iter) = stack.last_mut() {
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if let Some(&value) = iter.next() {
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let value = f.dfg.resolve_aliases(value);
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log::trace!(" -> DFS reaches {}", value);
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trace!(" -> DFS reaches {}", value);
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if value_ir_uses[value] == ValueUseState::Multiple {
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// Truncate DFS here: no need to go further,
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// as whole subtree must already be Multiple.
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@@ -658,7 +658,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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continue;
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}
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value_ir_uses[value] = ValueUseState::Multiple;
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log::trace!(" -> became Multiple");
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trace!(" -> became Multiple");
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push_args_on_stack(stack, value);
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} else {
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// Empty iterator, discard.
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@@ -683,7 +683,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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let arg = f.dfg.resolve_aliases(arg);
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let old = value_ir_uses[arg];
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if force_multiple {
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log::trace!(
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trace!(
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"forcing arg {} to Multiple because of multiple results of user inst",
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arg
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);
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@@ -692,7 +692,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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value_ir_uses[arg].inc();
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}
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let new = value_ir_uses[arg];
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log::trace!("arg {} used, old state {:?}, new {:?}", arg, old, new,);
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trace!("arg {} used, old state {:?}, new {:?}", arg, old, new,);
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// On transition to Multiple, do DFS.
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if old != ValueUseState::Multiple && new == ValueUseState::Multiple {
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push_args_on_stack(&mut stack, arg);
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@@ -706,7 +706,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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fn gen_arg_setup(&mut self) {
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if let Some(entry_bb) = self.f.layout.entry_block() {
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log::trace!(
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trace!(
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"gen_arg_setup: entry BB {} args are:\n{:?}",
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entry_bb,
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self.f.dfg.block_params(entry_bb)
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@@ -830,7 +830,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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}
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// Are any outputs used at least once?
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let value_needed = self.is_any_inst_result_needed(inst);
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log::trace!(
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trace!(
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"lower_clif_block: block {} inst {} ({:?}) is_branch {} side_effect {} value_needed {}",
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block,
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inst,
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@@ -860,7 +860,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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// Normal instruction: codegen if the instruction is side-effecting
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// or any of its outputs its used.
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if has_side_effect || value_needed {
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log::trace!("lowering: inst {}: {:?}", inst, self.f.dfg[inst]);
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trace!("lowering: inst {}: {:?}", inst, self.f.dfg[inst]);
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backend.lower(self, inst)?;
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}
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if data.opcode().is_return() {
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@@ -905,7 +905,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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fn get_value_labels<'a>(&'a self, val: Value, depth: usize) -> Option<&'a [ValueLabelStart]> {
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if let Some(ref values_labels) = self.f.dfg.values_labels {
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log::trace!(
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trace!(
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"get_value_labels: val {} -> {} -> {:?}",
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val,
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self.f.dfg.resolve_aliases(val),
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@@ -937,7 +937,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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.map(|&ValueLabelStart { label, .. }| label)
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.collect::<FxHashSet<_>>();
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for label in labels {
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log::trace!(
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trace!(
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"value labeling: defines val {:?} -> reg {:?} -> label {:?}",
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val,
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reg,
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@@ -953,7 +953,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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return;
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}
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log::trace!(
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trace!(
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"value labeling: srcloc {}: inst {}",
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self.srcloc(inst),
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inst
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@@ -968,7 +968,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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return;
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}
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log::trace!("value labeling: block {}", block);
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trace!("value labeling: block {}", block);
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for &arg in self.f.dfg.block_params(block) {
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self.emit_value_label_marks_for_value(arg);
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}
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@@ -999,7 +999,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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branches: &SmallVec<[Inst; 2]>,
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targets: &SmallVec<[MachLabel; 2]>,
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) -> CodegenResult<()> {
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log::trace!(
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trace!(
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"lower_clif_branches: block {} branches {:?} targets {:?}",
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block,
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branches,
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@@ -1061,7 +1061,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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/// Lower the function.
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pub fn lower<B: LowerBackend<MInst = I>>(mut self, backend: &B) -> CodegenResult<VCode<I>> {
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log::trace!("about to lower function: {:?}", self.f);
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trace!("about to lower function: {:?}", self.f);
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// Initialize the ABI object, giving it a temp if requested.
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let maybe_tmp = if let Some(temp_ty) = self.vcode.abi().temp_needed() {
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@@ -1152,7 +1152,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
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// Now that we've emitted all instructions into the
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// VCodeBuilder, let's build the VCode.
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let vcode = self.vcode.build();
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log::trace!("built vcode: {:?}", vcode);
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trace!("built vcode: {:?}", vcode);
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Ok(vcode)
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}
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@@ -1287,7 +1287,7 @@ impl<'func, I: VCodeInst> LowerCtx for Lower<'func, I> {
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}
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fn get_value_as_source_or_const(&self, val: Value) -> NonRegInput {
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log::trace!(
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trace!(
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"get_input_for_val: val {} at cur_inst {:?} cur_scan_entry_color {:?}",
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val,
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self.cur_inst,
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@@ -1317,8 +1317,8 @@ impl<'func, I: VCodeInst> LowerCtx for Lower<'func, I> {
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// prior to the sunk instruction) to sink.
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ValueDef::Result(src_inst, result_idx) => {
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let src_side_effect = has_lowering_side_effect(self.f, src_inst);
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log::trace!(" -> src inst {}", src_inst);
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log::trace!(" -> has lowering side effect: {}", src_side_effect);
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trace!(" -> src inst {}", src_inst);
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trace!(" -> has lowering side effect: {}", src_side_effect);
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if !src_side_effect {
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// Pure instruction: always possible to
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// sink. Let's determine whether we are the only
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@@ -1332,7 +1332,7 @@ impl<'func, I: VCodeInst> LowerCtx for Lower<'func, I> {
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// Side-effect: test whether this is the only use of the
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// only result of the instruction, and whether colors allow
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// the code-motion.
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log::trace!(
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trace!(
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" -> side-effecting op {} for val {}: use state {:?}",
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src_inst,
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val,
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@@ -1369,7 +1369,7 @@ impl<'func, I: VCodeInst> LowerCtx for Lower<'func, I> {
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fn put_value_in_regs(&mut self, val: Value) -> ValueRegs<Reg> {
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let val = self.f.dfg.resolve_aliases(val);
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log::trace!("put_value_in_regs: val {}", val);
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trace!("put_value_in_regs: val {}", val);
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// Assert that the value is not `iflags`/`fflags`-typed; these
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// cannot be reified into normal registers. TODO(#3249)
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@@ -1387,7 +1387,7 @@ impl<'func, I: VCodeInst> LowerCtx for Lower<'func, I> {
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.and_then(|inst| self.get_constant(inst))
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{
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let regs = self.alloc_tmp(ty);
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log::trace!(" -> regs {:?}", regs);
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trace!(" -> regs {:?}", regs);
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assert!(regs.is_valid());
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let insts = I::gen_constant(regs, c.into(), ty, |ty| {
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@@ -1400,7 +1400,7 @@ impl<'func, I: VCodeInst> LowerCtx for Lower<'func, I> {
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}
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let mut regs = self.value_regs[val];
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log::trace!(" -> regs {:?}", regs);
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trace!(" -> regs {:?}", regs);
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assert!(regs.is_valid());
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self.value_lowered_uses[val] += 1;
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@@ -1431,7 +1431,7 @@ impl<'func, I: VCodeInst> LowerCtx for Lower<'func, I> {
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}
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fn emit(&mut self, mach_inst: I) {
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log::trace!("emit: {:?}", mach_inst);
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trace!("emit: {:?}", mach_inst);
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self.ir_insts.push(mach_inst);
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}
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@@ -1492,7 +1492,7 @@ impl<'func, I: VCodeInst> LowerCtx for Lower<'func, I> {
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}
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fn set_vreg_alias(&mut self, from: Reg, to: Reg) {
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log::trace!("set vreg alias: from {:?} to {:?}", from, to);
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trace!("set vreg alias: from {:?} to {:?}", from, to);
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self.vcode.set_vreg_alias(from, to);
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}
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}
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