cranelift: Introduce a feature to enable trace logs (#4484)
* Don't use `log::trace` directly but a feature-enabled `trace` macro * Don't emit disassembly based on the log level
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@@ -7,6 +7,7 @@ use crate::ir::types::*;
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use crate::ir::{LibCall, MemFlags, TrapCode};
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use crate::isa::aarch64::inst::*;
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use crate::machinst::{ty_bits, Reg, RegClass, Writable};
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use crate::trace;
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use core::convert::TryFrom;
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/// Memory label/reference finalization: convert a MemLabel to a PC-relative
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@@ -39,7 +40,7 @@ pub fn mem_finalize(
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};
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let adj = match mem {
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&AMode::NominalSPOffset(..) => {
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log::trace!(
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trace!(
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"mem_finalize: nominal SP offset {} + adj {} -> {}",
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off,
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state.virtual_sp_offset,
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@@ -3068,7 +3069,7 @@ impl MachInstEmit for Inst {
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}
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}
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&Inst::VirtualSPOffsetAdj { offset } => {
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log::trace!(
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trace!(
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"virtual sp offset adjusted by {} -> {}",
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offset,
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state.virtual_sp_offset + offset,
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@@ -16,8 +16,8 @@ use crate::ir::{Opcode, Type, Value};
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use crate::isa::aarch64::inst::*;
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use crate::isa::aarch64::AArch64Backend;
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use crate::machinst::lower::*;
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use crate::machinst::*;
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use crate::machinst::{Reg, Writable};
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use crate::{machinst::*, trace};
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use crate::{CodegenError, CodegenResult};
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use smallvec::SmallVec;
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use std::cmp;
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@@ -236,7 +236,7 @@ fn lower_value_to_regs<C: LowerCtx<I = Inst>>(
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ctx: &mut C,
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value: Value,
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) -> (ValueRegs<Reg>, Type, bool) {
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log::trace!("lower_value_to_regs: value {:?}", value);
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trace!("lower_value_to_regs: value {:?}", value);
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let ty = ctx.value_ty(value);
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let inputs = ctx.get_value_as_source_or_const(value);
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let is_const = inputs.constant.is_some();
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@@ -608,7 +608,7 @@ pub(crate) fn lower_pair_address<C: LowerCtx<I = Inst>>(
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let (mut addends64, mut addends32, args_offset) = collect_address_addends(ctx, roots);
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let offset = args_offset + (offset as i64);
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log::trace!(
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trace!(
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"lower_pair_address: addends64 {:?}, addends32 {:?}, offset {}",
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addends64,
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addends32,
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@@ -669,7 +669,7 @@ pub(crate) fn lower_address<C: LowerCtx<I = Inst>>(
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let (mut addends64, mut addends32, args_offset) = collect_address_addends(ctx, roots);
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let mut offset = args_offset + (offset as i64);
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log::trace!(
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trace!(
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"lower_address: addends64 {:?}, addends32 {:?}, offset {}",
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addends64,
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addends32,
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@@ -1120,7 +1120,7 @@ pub(crate) fn maybe_input_insn<C: LowerCtx<I = Inst>>(
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op: Opcode,
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) -> Option<IRInst> {
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let inputs = c.get_input_as_source_or_const(input.insn, input.input);
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log::trace!(
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trace!(
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"maybe_input_insn: input {:?} has options {:?}; looking for op {:?}",
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input,
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inputs,
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@@ -1128,7 +1128,7 @@ pub(crate) fn maybe_input_insn<C: LowerCtx<I = Inst>>(
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);
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if let Some((src_inst, _)) = inputs.inst.as_inst() {
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let data = c.data(src_inst);
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log::trace!(" -> input inst {:?}", data);
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trace!(" -> input inst {:?}", data);
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if data.opcode() == op {
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return Some(src_inst);
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}
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@@ -1228,7 +1228,7 @@ pub(crate) fn lower_icmp<C: LowerCtx<I = Inst>>(
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condcode: IntCC,
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output: IcmpOutput,
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) -> CodegenResult<IcmpResult> {
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log::trace!(
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trace!(
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"lower_icmp: insn {}, condcode: {}, output: {:?}",
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insn,
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condcode,
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@@ -73,7 +73,6 @@ impl TargetIsa for AArch64Backend {
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let flags = self.flags();
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let (vcode, regalloc_result) = self.compile_vcode(func, flags.clone())?;
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let want_disasm = want_disasm || log::log_enabled!(log::Level::Debug);
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let emit_result = vcode.emit(®alloc_result, want_disasm, flags.machine_code_cfg_info());
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let frame_size = emit_result.frame_size;
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let value_labels_ranges = emit_result.value_labels_ranges;
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