Add a regmove instruction.
This will be used to locally change the register locations of values in order to satisfy instruction constraints.
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@@ -9,6 +9,7 @@ use ir::{Opcode, Type, Inst, Value, Ebb, JumpTable, SigRef, FuncRef, StackSlot,
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MemFlags};
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use ir::immediates::{Imm64, Uimm8, Ieee32, Ieee64, Offset32, Uoffset32};
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use ir::condcodes::{IntCC, FloatCC};
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use isa::RegUnit;
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/// Base trait for instruction builders.
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///
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@@ -687,7 +687,7 @@ impl<'a> fmt::Display for DisplayInst<'a> {
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} else {
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write!(f, "{}.{}", inst.opcode(), typevar)?;
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}
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write_operands(f, dfg, self.1)
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write_operands(f, dfg, None, self.1)
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}
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}
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@@ -14,6 +14,7 @@ use ir::{Value, Type, Ebb, JumpTable, SigRef, FuncRef, StackSlot, MemFlags};
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use ir::immediates::{Imm64, Uimm8, Ieee32, Ieee64, Offset32, Uoffset32};
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use ir::condcodes::*;
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use ir::types;
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use isa::RegUnit;
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use entity_list;
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use ref_slice::{ref_slice, ref_slice_mut};
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@@ -203,6 +204,12 @@ pub enum InstructionData {
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args: [Value; 2],
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offset: Offset32,
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},
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RegMove {
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opcode: Opcode,
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arg: Value,
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src: RegUnit,
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dst: RegUnit,
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},
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}
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/// A variable list of `Value` operands used for function call arguments and passing arguments to
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@@ -284,7 +284,8 @@ impl<'a> Verifier<'a> {
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&HeapLoad { .. } |
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&HeapStore { .. } |
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&Load { .. } |
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&Store { .. } => {}
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&Store { .. } |
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&RegMove { .. } => {}
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}
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Ok(())
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@@ -225,12 +225,16 @@ fn write_instruction(w: &mut Write,
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None => write!(w, "{}", opcode)?,
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}
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write_operands(w, &func.dfg, inst)?;
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write_operands(w, &func.dfg, isa, inst)?;
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writeln!(w, "")
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}
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/// Write the operands of `inst` to `w` with a prepended space.
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pub fn write_operands(w: &mut Write, dfg: &DataFlowGraph, inst: Inst) -> Result {
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pub fn write_operands(w: &mut Write,
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dfg: &DataFlowGraph,
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isa: Option<&TargetIsa>,
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inst: Inst)
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-> Result {
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let pool = &dfg.value_lists;
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use ir::instructions::InstructionData::*;
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match dfg[inst] {
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@@ -321,6 +325,19 @@ pub fn write_operands(w: &mut Write, dfg: &DataFlowGraph, inst: Inst) -> Result
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offset,
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..
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} => write!(w, "{} {}, {}{}", flags, args[0], args[1], offset),
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RegMove { arg, src, dst, .. } => {
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if let Some(isa) = isa {
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let regs = isa.register_info();
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write!(w,
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" {}, {} -> {}",
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arg,
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regs.display_regunit(src),
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regs.display_regunit(dst))
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} else {
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write!(w, " {}, %{} -> %{}", arg, src, dst)
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}
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}
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}
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}
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