Add support for packed float to signed int conversion

Implements i32x4.trunc_sat_f32x4_s

cranelift/codegen/src/isa/x64/inst/args.rs

@@ -371,6 +371,7 @@ pub enum SseOpcode {
     Cvtsi2sd,
     Cvtss2si,
     Cvtss2sd,
+    Cvttps2dq,
     Cvttss2si,
     Cvttsd2si,
     Divps,
@@ -535,6 +536,7 @@ impl SseOpcode {
             | SseOpcode::Cvtsd2si
             | SseOpcode::Cvtsi2sd
             | SseOpcode::Cvtss2sd
+            | SseOpcode::Cvttps2dq
             | SseOpcode::Cvttsd2si
             | SseOpcode::Divpd
             | SseOpcode::Divsd
@@ -662,6 +664,7 @@ impl fmt::Debug for SseOpcode {
             SseOpcode::Cvtsi2sd => "cvtsi2sd",
             SseOpcode::Cvtss2si => "cvtss2si",
             SseOpcode::Cvtss2sd => "cvtss2sd",
+            SseOpcode::Cvttps2dq => "cvttps2dq",
             SseOpcode::Cvttss2si => "cvttss2si",
             SseOpcode::Cvttsd2si => "cvttsd2si",
             SseOpcode::Divps => "divps",