x64: Lower widening and narrowing operations in ISLE (#4722)
Lower uwiden_high, uwiden_low, swiden_high, swiden_low, snarrow, and unarrow in ISLE.
This commit is contained in:
Trevor Elliott
@@ -562,216 +562,16 @@ fn lower_insn_to_regs(
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| Opcode::FcvtToSint
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| Opcode::FcvtToUintSat
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| Opcode::FcvtToSintSat
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| Opcode::IaddPairwise => {
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| Opcode::IaddPairwise
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| Opcode::UwidenHigh
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| Opcode::UwidenLow
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| Opcode::SwidenHigh
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| Opcode::SwidenLow
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| Opcode::Snarrow
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| Opcode::Unarrow => {
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implemented_in_isle(ctx);
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}
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Opcode::UwidenHigh | Opcode::UwidenLow | Opcode::SwidenHigh | Opcode::SwidenLow => {
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let input_ty = ctx.input_ty(insn, 0);
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let output_ty = ctx.output_ty(insn, 0);
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let src = put_input_in_reg(ctx, inputs[0]);
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let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
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if output_ty.is_vector() {
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match op {
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Opcode::SwidenLow => match (input_ty, output_ty) {
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(types::I8X16, types::I16X8) => {
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ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxbw, RegMem::reg(src), dst));
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}
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(types::I16X8, types::I32X4) => {
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ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxwd, RegMem::reg(src), dst));
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}
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(types::I32X4, types::I64X2) => {
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ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxdq, RegMem::reg(src), dst));
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}
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_ => unreachable!(),
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},
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Opcode::SwidenHigh => match (input_ty, output_ty) {
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(types::I8X16, types::I16X8) => {
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ctx.emit(Inst::gen_move(dst, src, output_ty));
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ctx.emit(Inst::xmm_rm_r_imm(
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SseOpcode::Palignr,
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RegMem::reg(src),
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dst,
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8,
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OperandSize::Size32,
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));
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ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxbw, RegMem::from(dst), dst));
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}
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(types::I16X8, types::I32X4) => {
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ctx.emit(Inst::gen_move(dst, src, output_ty));
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ctx.emit(Inst::xmm_rm_r_imm(
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SseOpcode::Palignr,
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RegMem::reg(src),
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dst,
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8,
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OperandSize::Size32,
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));
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ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxwd, RegMem::from(dst), dst));
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}
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(types::I32X4, types::I64X2) => {
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ctx.emit(Inst::xmm_rm_r_imm(
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SseOpcode::Pshufd,
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RegMem::reg(src),
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dst,
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0xEE,
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OperandSize::Size32,
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));
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ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxdq, RegMem::from(dst), dst));
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}
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_ => unreachable!(),
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},
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Opcode::UwidenLow => match (input_ty, output_ty) {
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(types::I8X16, types::I16X8) => {
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ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxbw, RegMem::reg(src), dst));
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}
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(types::I16X8, types::I32X4) => {
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ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxwd, RegMem::reg(src), dst));
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}
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(types::I32X4, types::I64X2) => {
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ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxdq, RegMem::reg(src), dst));
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}
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_ => unreachable!(),
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},
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Opcode::UwidenHigh => match (input_ty, output_ty) {
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(types::I8X16, types::I16X8) => {
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ctx.emit(Inst::gen_move(dst, src, output_ty));
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ctx.emit(Inst::xmm_rm_r_imm(
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SseOpcode::Palignr,
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RegMem::reg(src),
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dst,
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8,
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OperandSize::Size32,
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));
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ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxbw, RegMem::from(dst), dst));
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}
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(types::I16X8, types::I32X4) => {
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ctx.emit(Inst::gen_move(dst, src, output_ty));
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ctx.emit(Inst::xmm_rm_r_imm(
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SseOpcode::Palignr,
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RegMem::reg(src),
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dst,
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8,
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OperandSize::Size32,
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));
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ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxwd, RegMem::from(dst), dst));
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}
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(types::I32X4, types::I64X2) => {
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ctx.emit(Inst::xmm_rm_r_imm(
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SseOpcode::Pshufd,
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RegMem::reg(src),
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dst,
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0xEE,
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OperandSize::Size32,
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));
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ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxdq, RegMem::from(dst), dst));
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}
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_ => unreachable!(),
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},
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_ => unreachable!(),
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}
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} else {
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panic!("Unsupported non-vector type for widen instruction {:?}", ty);
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}
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}
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Opcode::Snarrow | Opcode::Unarrow => {
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let input_ty = ctx.input_ty(insn, 0);
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let output_ty = ctx.output_ty(insn, 0);
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let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
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if output_ty.is_vector() {
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match op {
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Opcode::Snarrow => match (input_ty, output_ty) {
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(types::I16X8, types::I8X16) => {
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let src1 = put_input_in_reg(ctx, inputs[0]);
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let src2 = put_input_in_reg(ctx, inputs[1]);
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ctx.emit(Inst::gen_move(dst, src1, input_ty));
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ctx.emit(Inst::xmm_rm_r(SseOpcode::Packsswb, RegMem::reg(src2), dst));
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}
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(types::I32X4, types::I16X8) => {
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let src1 = put_input_in_reg(ctx, inputs[0]);
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let src2 = put_input_in_reg(ctx, inputs[1]);
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ctx.emit(Inst::gen_move(dst, src1, input_ty));
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ctx.emit(Inst::xmm_rm_r(SseOpcode::Packssdw, RegMem::reg(src2), dst));
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}
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// TODO: The type we are expecting as input as actually an F64X2 but the instruction is only defined
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// for integers so here we use I64X2. This is a separate issue that needs to be fixed in instruction.rs.
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(types::I64X2, types::I32X4) => {
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if let Some(fcvt_inst) =
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matches_input(ctx, inputs[0], Opcode::FcvtToSintSat)
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{
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//y = i32x4.trunc_sat_f64x2_s_zero(x) is lowered to:
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//MOVE xmm_tmp, xmm_x
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//CMPEQPD xmm_tmp, xmm_x
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//MOVE xmm_y, xmm_x
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//ANDPS xmm_tmp, [wasm_f64x2_splat(2147483647.0)]
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//MINPD xmm_y, xmm_tmp
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//CVTTPD2DQ xmm_y, xmm_y
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let fcvt_input = InsnInput {
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insn: fcvt_inst,
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input: 0,
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};
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let src = put_input_in_reg(ctx, fcvt_input);
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ctx.emit(Inst::gen_move(dst, src, input_ty));
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let tmp1 = ctx.alloc_tmp(output_ty).only_reg().unwrap();
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ctx.emit(Inst::gen_move(tmp1, src, input_ty));
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let cond = FcmpImm::from(FloatCC::Equal);
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ctx.emit(Inst::xmm_rm_r_imm(
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SseOpcode::Cmppd,
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RegMem::reg(src),
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tmp1,
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cond.encode(),
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OperandSize::Size32,
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));
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// 2147483647.0 is equivalent to 0x41DFFFFFFFC00000
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static UMAX_MASK: [u8; 16] = [
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0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xDF, 0x41, 0x00, 0x00,
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0xC0, 0xFF, 0xFF, 0xFF, 0xDF, 0x41,
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];
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let umax_const =
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ctx.use_constant(VCodeConstantData::WellKnown(&UMAX_MASK));
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let umax_mask = ctx.alloc_tmp(types::F64X2).only_reg().unwrap();
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ctx.emit(Inst::xmm_load_const(umax_const, umax_mask, types::F64X2));
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//ANDPD xmm_y, [wasm_f64x2_splat(2147483647.0)]
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ctx.emit(Inst::xmm_rm_r(
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SseOpcode::Andps,
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RegMem::from(umax_mask),
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tmp1,
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));
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ctx.emit(Inst::xmm_rm_r(SseOpcode::Minpd, RegMem::from(tmp1), dst));
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ctx.emit(Inst::xmm_unary_rm_r(
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SseOpcode::Cvttpd2dq,
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RegMem::from(dst),
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dst,
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));
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} else {
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unreachable!();
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}
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}
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_ => unreachable!(),
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},
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Opcode::Unarrow => match (input_ty, output_ty) {
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(types::I16X8, types::I8X16) => {
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let src1 = put_input_in_reg(ctx, inputs[0]);
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let src2 = put_input_in_reg(ctx, inputs[1]);
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ctx.emit(Inst::gen_move(dst, src1, input_ty));
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ctx.emit(Inst::xmm_rm_r(SseOpcode::Packuswb, RegMem::reg(src2), dst));
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}
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(types::I32X4, types::I16X8) => {
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let src1 = put_input_in_reg(ctx, inputs[0]);
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let src2 = put_input_in_reg(ctx, inputs[1]);
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ctx.emit(Inst::gen_move(dst, src1, input_ty));
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ctx.emit(Inst::xmm_rm_r(SseOpcode::Packusdw, RegMem::reg(src2), dst));
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}
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_ => unreachable!(),
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},
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_ => unreachable!(),
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}
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} else {
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panic!("Unsupported non-vector type for widen instruction {:?}", ty);
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}
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}
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Opcode::Bitcast => {
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let input_ty = ctx.input_ty(insn, 0);
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let output_ty = ctx.output_ty(insn, 0);
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