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carolinecullen
2019-03-12 08:21:35 -07:00
committed by Dan Gohman
parent 72bc035d70
commit 8ab7170a07
1 changed files with 2 additions and 10 deletions
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12
cranelift/codegen/src/isa/arm32/abi.rs
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@@ -39,7 +39,7 @@ impl ArgAssigner for Args {
let ty = arg.value_type; let ty = arg.value_type;
// Check for a legal type. // Check for a legal type.
// RISC-V doesn't have SIMD at all, so break all vectors down. // SIMD instructions are currently no implemented, so break down vectors
if ty.is_vector() { if ty.is_vector() {
return ValueConversion::VectorSplit.into(); return ValueConversion::VectorSplit.into();
} }
@@ -116,13 +116,5 @@ pub fn regclass_for_abi_type(ty: ir::Type) -> RegClass {
/// Get the set of allocatable registers for `func`. /// Get the set of allocatable registers for `func`.
pub fn allocatable_registers(_func: &ir::Function) -> RegisterSet { pub fn allocatable_registers(_func: &ir::Function) -> RegisterSet {
let mut regs = RegisterSet::new(); unimplemented!()
regs.take(GPR, GPR.unit(0)); // Hard-wired 0.
// %x1 is the link register which is available for allocation.
regs.take(GPR, GPR.unit(2)); // Stack pointer.
regs.take(GPR, GPR.unit(3)); // Global pointer.
regs.take(GPR, GPR.unit(4)); // Thread pointer.
// TODO: %x8 is the frame pointer. Reserve it?
regs
} }