From 8a6686ec45ebf7a26034b8f3b97499bd720e0eee Mon Sep 17 00:00:00 2001
From: Andrew Brown <andrew.brown@intel.com>
Date: Wed, 21 Aug 2019 14:59:17 -0700
Subject: [PATCH] Enable SSSE3 setting when detected on CPU

---
 cranelift/native/src/lib.rs | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/cranelift/native/src/lib.rs b/cranelift/native/src/lib.rs
index 0687e70173..cfa27cef86 100644
--- a/cranelift/native/src/lib.rs
+++ b/cranelift/native/src/lib.rs
@@ -59,6 +59,9 @@ fn parse_x86_cpuid(isa_builder: &mut isa::Builder) -> Result<(), &'static str> {
         if info.has_sse3() {
             isa_builder.enable("has_sse3").unwrap();
         }
+        if info.has_ssse3() {
+            isa_builder.enable("has_ssse3").unwrap();
+        }
         if info.has_sse41() {
             isa_builder.enable("has_sse41").unwrap();
         }