Support IBM z/Architecture

This adds support for the IBM z/Architecture (s390x-ibm-linux).

The status of the s390x backend in its current form is:
- Wasmtime is fully functional and passes all tests on s390x.
- All back-end features supported, with the exception of SIMD.
- There is still a lot of potential for performance improvements.
- Currently the only supported processor type is z15.

cranelift/filetests/filetests/isa/s390x/bitops.clif

@@ -0,0 +1,243 @@
+test compile
+target s390x
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; BITREV
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; FIXME: bitrev not yet implemented
+
+;function %bitrev_i64(i64) -> i64 {
+;block0(v0: i64):
+;    v1 = bitrev v0
+;    return v1
+;}
+;
+;function %bitrev_i32(i32) -> i32 {
+;block0(v0: i32):
+;    v1 = bitrev v0
+;    return v1
+;}
+;
+;function %bitrev_i16(i16) -> i16 {
+;block0(v0: i16):
+;    v1 = bitrev v0
+;    return v1
+;}
+;
+;function %bitrev_i8(i8) -> i8 {
+;block0(v0: i8):
+;    v1 = bitrev v0
+;    return v1
+;}
+;
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; CLZ
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %clz_i64(i64) -> i64 {
+block0(v0: i64):
+    v1 = clz v0
+    return v1
+}
+
+; check:  flogr %r0, %r2
+; nextln: lgr %r2, %r0
+; nextln: br %r14
+
+function %clz_i32(i32) -> i32 {
+block0(v0: i32):
+    v1 = clz v0
+    return v1
+}
+
+; check:  llgfr %r2, %r2
+; nextln: flogr %r0, %r2
+; nextln: lr %r2, %r0
+; nextln: ahi %r2, -32
+; nextln: br %r14
+
+function %clz_i16(i16) -> i16 {
+block0(v0: i16):
+    v1 = clz v0
+    return v1
+}
+
+; check:  llghr %r2, %r2
+; nextln: flogr %r0, %r2
+; nextln: lr %r2, %r0
+; nextln: ahi %r2, -48
+; nextln: br %r14
+
+function %clz_i8(i8) -> i8 {
+block0(v0: i8):
+    v1 = clz v0
+    return v1
+}
+
+; check:  llgcr %r2, %r2
+; nextln: flogr %r0, %r2
+; nextln: lr %r2, %r0
+; nextln: ahi %r2, -56
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; CLS
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %cls_i64(i64) -> i64 {
+block0(v0: i64):
+    v1 = cls v0
+    return v1
+}
+
+; check:  srag %r3, %r2, 63
+; nextln: xgr %r3, %r2
+; nextln: flogr %r0, %r2
+; nextln: lgr %r2, %r0
+; nextln: br %r14
+
+function %cls_i32(i32) -> i32 {
+block0(v0: i32):
+    v1 = cls v0
+    return v1
+}
+
+; check:  lgfr %r2, %r2
+; nextln: srag %r3, %r2, 63
+; nextln: xgr %r3, %r2
+; nextln: flogr %r0, %r2
+; nextln: lr %r2, %r0
+; nextln: ahi %r2, -32
+; nextln: br %r14
+
+function %cls_i16(i16) -> i16 {
+block0(v0: i16):
+    v1 = cls v0
+    return v1
+}
+
+; check:  lghr %r2, %r2
+; nextln: srag %r3, %r2, 63
+; nextln: xgr %r3, %r2
+; nextln: flogr %r0, %r2
+; nextln: lr %r2, %r0
+; nextln: ahi %r2, -48
+; nextln: br %r14
+
+function %cls_i8(i8) -> i8 {
+block0(v0: i8):
+    v1 = cls v0
+    return v1
+}
+
+; check:  lgbr %r2, %r2
+; nextln: srag %r3, %r2, 63
+; nextln: xgr %r3, %r2
+; nextln: flogr %r0, %r2
+; nextln: lr %r2, %r0
+; nextln: ahi %r2, -56
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; CTZ
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %ctz_i64(i64) -> i64 {
+block0(v0: i64):
+    v1 = ctz v0
+    return v1
+}
+
+; check:  lcgr %r3, %r2
+; nextln: ngrk %r2, %r3, %r2
+; nextln: flogr %r0, %r2
+; nextln: locghie %r0, -1
+; nextln: lghi %r2, 63
+; nextln: sgr %r2, %r0
+; nextln: br %r14
+
+function %ctz_i32(i32) -> i32 {
+block0(v0: i32):
+    v1 = ctz v0
+    return v1
+}
+
+; check:  oihl %r2, 1
+; nextln: lcgr %r3, %r2
+; nextln: ngrk %r2, %r3, %r2
+; nextln: flogr %r0, %r2
+; nextln: lhi %r2, 63
+; nextln: sr %r2, %r0
+; nextln: br %r14
+
+function %ctz_i16(i16) -> i16 {
+block0(v0: i16):
+    v1 = ctz v0
+    return v1
+}
+
+; check:  oilh %r2, 1
+; nextln: lcgr %r3, %r2
+; nextln: ngrk %r2, %r3, %r2
+; nextln: flogr %r0, %r2
+; nextln: lhi %r2, 63
+; nextln: sr %r2, %r0
+; nextln: br %r14
+
+function %ctz_i8(i8) -> i8 {
+block0(v0: i8):
+    v1 = ctz v0
+    return v1
+}
+
+; check:  oill %r2, 256
+; nextln: lcgr %r3, %r2
+; nextln: ngrk %r2, %r3, %r2
+; nextln: flogr %r0, %r2
+; nextln: lhi %r2, 63
+; nextln: sr %r2, %r0
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; POPCNT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %popcnt_i64(i64) -> i64 {
+block0(v0: i64):
+    v1 = popcnt v0
+    return v1
+}
+
+; check:  popcnt %r2, %r2, 8
+; nextln: br %r14
+
+function %popcnt_i32(i32) -> i32 {
+block0(v0: i32):
+    v1 = popcnt v0
+    return v1
+}
+
+; check:  llgfr %r2, %r2
+; nextln: popcnt %r2, %r2, 8
+; nextln: br %r14
+
+function %popcnt_i16(i16) -> i16 {
+block0(v0: i16):
+    v1 = popcnt v0
+    return v1
+}
+
+; check:  llghr %r2, %r2
+; nextln: popcnt %r2, %r2, 8
+; nextln: br %r14
+
+function %popcnt_i8(i8) -> i8 {
+block0(v0: i8):
+    v1 = popcnt v0
+    return v1
+}
+
+; check: popcnt %r2, %r2
+; nextln: br %r14

cranelift/filetests/filetests/isa/s390x/bitwise.clif

@@ -0,0 +1,490 @@
+
+test compile
+target s390x
+
+; FIXME: add immediate operand versions
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; BAND
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %band_i64(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = band.i64 v0, v1
+  return v2
+}
+
+; check:  ngr %r2, %r3
+; nextln: br %r14
+
+function %band_i64_mem(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = load.i64 v1
+  v3 = band.i64 v0, v2
+  return v3
+}
+
+; check:  ng %r2, 0(%r3)
+; nextln: br %r14
+
+function %band_i32(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = band.i32 v0, v1
+  return v2
+}
+
+; check:  nr %r2, %r3
+; nextln: br %r14
+
+function %band_i32_mem(i32, i64) -> i32 {
+block0(v0: i32, v1: i64):
+  v2 = load.i32 v1
+  v3 = band.i32 v0, v2
+  return v3
+}
+
+; check:  n %r2, 0(%r3)
+; nextln: br %r14
+
+function %band_i32_memoff(i32, i64) -> i32 {
+block0(v0: i32, v1: i64):
+  v2 = load.i32 v1+4096
+  v3 = band.i32 v0, v2
+  return v3
+}
+
+; check:  ny %r2, 4096(%r3)
+; nextln: br %r14
+
+function %band_i16(i16, i16) -> i16 {
+block0(v0: i16, v1: i16):
+  v2 = band.i16 v0, v1
+  return v2
+}
+
+; check:  nr %r2, %r3
+; nextln: br %r14
+
+function %band_i16_mem(i16, i64) -> i16 {
+block0(v0: i16, v1: i64):
+  v2 = load.i16 v1
+  v3 = band.i16 v0, v2
+  return v3
+}
+
+; check:  llh %r3, 0(%r3)
+; nextln: nr %r2, %r3
+; nextln: br %r14
+
+function %band_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+  v2 = band.i8 v0, v1
+  return v2
+}
+
+; check:  nr %r2, %r3
+; nextln: br %r14
+
+function %band_i8_mem(i8, i64) -> i8 {
+block0(v0: i8, v1: i64):
+  v2 = load.i8 v1
+  v3 = band.i8 v0, v2
+  return v3
+}
+
+; check:  llc %r3, 0(%r3)
+; nextln: nr %r2, %r3
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; BOR
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %bor_i64(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = bor.i64 v0, v1
+  return v2
+}
+
+; check:  ogr %r2, %r3
+; nextln: br %r14
+
+function %bor_i64_mem(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = load.i64 v1
+  v3 = bor.i64 v0, v2
+  return v3
+}
+
+; check:  og %r2, 0(%r3)
+; nextln: br %r14
+
+function %bor_i32(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = bor.i32 v0, v1
+  return v2
+}
+
+; check:  or %r2, %r3
+; nextln: br %r14
+
+function %bor_i32_mem(i32, i64) -> i32 {
+block0(v0: i32, v1: i64):
+  v2 = load.i32 v1
+  v3 = bor.i32 v0, v2
+  return v3
+}
+
+; check:  o %r2, 0(%r3)
+; nextln: br %r14
+
+function %bor_i32_memoff(i32, i64) -> i32 {
+block0(v0: i32, v1: i64):
+  v2 = load.i32 v1+4096
+  v3 = bor.i32 v0, v2
+  return v3
+}
+
+; check:  oy %r2, 4096(%r3)
+; nextln: br %r14
+
+function %bor_i16(i16, i16) -> i16 {
+block0(v0: i16, v1: i16):
+  v2 = bor.i16 v0, v1
+  return v2
+}
+
+; check:  or %r2, %r3
+; nextln: br %r14
+
+function %bor_i16_mem(i16, i64) -> i16 {
+block0(v0: i16, v1: i64):
+  v2 = load.i16 v1
+  v3 = bor.i16 v0, v2
+  return v3
+}
+
+; check:  llh %r3, 0(%r3)
+; nextln: or %r2, %r3
+; nextln: br %r14
+
+function %bor_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+  v2 = bor.i8 v0, v1
+  return v2
+}
+
+; check:  or %r2, %r3
+; nextln: br %r14
+
+function %bor_i8_mem(i8, i64) -> i8 {
+block0(v0: i8, v1: i64):
+  v2 = load.i8 v1
+  v3 = bor.i8 v0, v2
+  return v3
+}
+
+; check:  llc %r3, 0(%r3)
+; nextln: or %r2, %r3
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; BXOR
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %bxor_i64(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = bxor.i64 v0, v1
+  return v2
+}
+
+; check:  xgr %r2, %r3
+; nextln: br %r14
+
+function %bxor_i64_mem(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = load.i64 v1
+  v3 = bxor.i64 v0, v2
+  return v3
+}
+
+; check:  xg %r2, 0(%r3)
+; nextln: br %r14
+
+function %bxor_i32(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = bxor.i32 v0, v1
+  return v2
+}
+
+; check:  xr %r2, %r3
+; nextln: br %r14
+
+function %bxor_i32_mem(i32, i64) -> i32 {
+block0(v0: i32, v1: i64):
+  v2 = load.i32 v1
+  v3 = bxor.i32 v0, v2
+  return v3
+}
+
+; check:  x %r2, 0(%r3)
+; nextln: br %r14
+
+function %bxor_i32_memoff(i32, i64) -> i32 {
+block0(v0: i32, v1: i64):
+  v2 = load.i32 v1+4096
+  v3 = bxor.i32 v0, v2
+  return v3
+}
+
+; check:  xy %r2, 4096(%r3)
+; nextln: br %r14
+
+function %bxor_i16(i16, i16) -> i16 {
+block0(v0: i16, v1: i16):
+  v2 = bxor.i16 v0, v1
+  return v2
+}
+
+; check:  xr %r2, %r3
+; nextln: br %r14
+
+function %bxor_i16_mem(i16, i64) -> i16 {
+block0(v0: i16, v1: i64):
+  v2 = load.i16 v1
+  v3 = bxor.i16 v0, v2
+  return v3
+}
+
+; check:  llh %r3, 0(%r3)
+; nextln: xr %r2, %r3
+; nextln: br %r14
+
+function %bxor_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+  v2 = bxor.i8 v0, v1
+  return v2
+}
+
+; check:  xr %r2, %r3
+; nextln: br %r14
+
+function %bxor_i8_mem(i8, i64) -> i8 {
+block0(v0: i8, v1: i64):
+  v2 = load.i8 v1
+  v3 = bxor.i8 v0, v2
+  return v3
+}
+
+; check:  llc %r3, 0(%r3)
+; nextln: xr %r2, %r3
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; BAND_NOT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %band_not_i64(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = band_not.i64 v0, v1
+  return v2
+}
+
+; check:  nngrk %r2, %r2, %r3
+; nextln: br %r14
+
+function %band_not_i32(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = band_not.i32 v0, v1
+  return v2
+}
+
+; check:  nnrk %r2, %r2, %r3
+; nextln: br %r14
+
+function %band_not_i16(i16, i16) -> i16 {
+block0(v0: i16, v1: i16):
+  v2 = band_not.i16 v0, v1
+  return v2
+}
+
+; check:  nnrk %r2, %r2, %r3
+; nextln: br %r14
+
+function %band_not_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+  v2 = band_not.i8 v0, v1
+  return v2
+}
+
+; check:  nnrk %r2, %r2, %r3
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; BOR_NOT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %bor_not_i64(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = bor_not.i64 v0, v1
+  return v2
+}
+
+; check:  nogrk %r2, %r2, %r3
+; nextln: br %r14
+
+function %bor_not_i32(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = bor_not.i32 v0, v1
+  return v2
+}
+
+; check:  nork %r2, %r2, %r3
+; nextln: br %r14
+
+function %bor_not_i16(i16, i16) -> i16 {
+block0(v0: i16, v1: i16):
+  v2 = bor_not.i16 v0, v1
+  return v2
+}
+
+; check:  nork %r2, %r2, %r3
+; nextln: br %r14
+
+function %bor_not_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+  v2 = bor_not.i8 v0, v1
+  return v2
+}
+
+; check:  nork %r2, %r2, %r3
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; BXOR_NOT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %bxor_not_i64(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = bxor_not.i64 v0, v1
+  return v2
+}
+
+; check:  nxgrk %r2, %r2, %r3
+; nextln: br %r14
+
+function %bxor_not_i32(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = bxor_not.i32 v0, v1
+  return v2
+}
+
+; check:  nxrk %r2, %r2, %r3
+; nextln: br %r14
+
+function %bxor_not_i16(i16, i16) -> i16 {
+block0(v0: i16, v1: i16):
+  v2 = bxor_not.i16 v0, v1
+  return v2
+}
+
+; check:  nxrk %r2, %r2, %r3
+; nextln: br %r14
+
+function %bxor_not_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+  v2 = bxor_not.i8 v0, v1
+  return v2
+}
+
+; check:  nxrk %r2, %r2, %r3
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; BNOT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %bnot_i64(i64) -> i64 {
+block0(v0: i64):
+  v1 = bnot.i64 v0
+  return v1
+}
+
+; check:  nogrk %r2, %r2, %r2
+; nextln: br %r14
+
+function %bnot_i32(i32) -> i32 {
+block0(v0: i32):
+  v1 = bnot.i32 v0
+  return v1
+}
+
+; check:  nork %r2, %r2, %r2
+; nextln: br %r14
+
+function %bnot_i16(i16) -> i16 {
+block0(v0: i16):
+  v1 = bnot.i16 v0
+  return v1
+}
+
+; check:  nork %r2, %r2, %r2
+; nextln: br %r14
+
+function %bnot_i8(i8) -> i8 {
+block0(v0: i8):
+  v1 = bnot.i8 v0
+  return v1
+}
+
+; check:  nork %r2, %r2, %r2
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; BITSELECT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %bitselect_i64(i64, i64, i64) -> i64 {
+block0(v0: i64, v1: i64, v2: i64):
+  v3 = bitselect.i64 v0, v1, v2
+  return v3
+}
+
+; check:  ngr %r3, %r2
+; nextln: nngrk %r2, %r4, %r2
+; nextln: ogr %r2, %r3
+; nextln: br %r14
+
+function %bitselect_i32(i32, i32, i32) -> i32 {
+block0(v0: i32, v1: i32, v2: i32):
+  v3 = bitselect.i32 v0, v1, v2
+  return v3
+}
+
+; check:  nr %r3, %r2
+; nextln: nnrk %r2, %r4, %r2
+; nextln: or %r2, %r3
+; nextln: br %r14
+
+function %bitselect_i16(i16, i16, i16) -> i16 {
+block0(v0: i16, v1: i16, v2: i16):
+  v3 = bitselect.i16 v0, v1, v2
+  return v3
+}
+
+; check:  nr %r3, %r2
+; nextln: nnrk %r2, %r4, %r2
+; nextln: or %r2, %r3
+; nextln: br %r14
+
+function %bitselect_i8(i8, i8, i8) -> i8 {
+block0(v0: i8, v1: i8, v2: i8):
+  v3 = bitselect.i8 v0, v1, v2
+  return v3
+}
+
+; check:  nr %r3, %r2
+; nextln: nnrk %r2, %r4, %r2
+; nextln: or %r2, %r3
+; nextln: br %r14
+

cranelift/filetests/filetests/isa/s390x/call.clif

@@ -0,0 +1,113 @@
+test compile
+target s390x
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; CALL
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %call(i64) -> i64 {
+    fn0 = %g(i64) -> i64
+
+block0(v0: i64):
+    v1 = call fn0(v0)
+    return v1
+}
+
+; check:  stmg %r14, %r15, 112(%r15)
+; nextln: aghi %r15, -160
+; nextln: virtual_sp_offset_adjust 160
+; nextln: bras %r1, 12 ; data %g + 0 ; lg %r3, 0(%r1)
+; nextln: basr %r14, %r3
+; nextln: lmg %r14, %r15, 272(%r15)
+; nextln: br %r14
+
+function %call_uext(i32) -> i64 {
+    fn0 = %g(i32 uext) -> i64
+
+block0(v0: i32):
+    v1 = call fn0(v0)
+    return v1
+}
+
+; check:  stmg %r14, %r15, 112(%r15)
+; nextln: aghi %r15, -160
+; nextln: virtual_sp_offset_adjust 160
+; nextln: llgfr %r2, %r2
+; nextln: bras %r1, 12 ; data %g + 0 ; lg %r3, 0(%r1)
+; nextln: basr %r14, %r3
+; nextln: lmg %r14, %r15, 272(%r15)
+; nextln: br %r14
+
+function %ret_uext(i32) -> i32 uext {
+block0(v0: i32):
+    return v0
+}
+
+; check:  llgfr %r2, %r2
+; nextln: br %r14
+
+function %call_uext(i32) -> i64 {
+    fn0 = %g(i32 sext) -> i64
+
+block0(v0: i32):
+    v1 = call fn0(v0)
+    return v1
+}
+
+; check:  stmg %r14, %r15, 112(%r15)
+; nextln: aghi %r15, -160
+; nextln: virtual_sp_offset_adjust 160
+; nextln: lgfr %r2, %r2
+; nextln: bras %r1, 12 ; data %g + 0 ; lg %r3, 0(%r1)
+; nextln: basr %r14, %r3
+; nextln: lmg %r14, %r15, 272(%r15)
+; nextln: br %r14
+
+function %ret_uext(i32) -> i32 sext {
+block0(v0: i32):
+    return v0
+}
+
+; check:  lgfr %r2, %r2
+; nextln: br %r14
+
+function %call_colocated(i64) -> i64 {
+    fn0 = colocated %g(i64) -> i64
+
+block0(v0: i64):
+    v1 = call fn0(v0)
+    return v1
+}
+
+; check:  stmg %r14, %r15, 112(%r15)
+; nextln: aghi %r15, -160
+; nextln: virtual_sp_offset_adjust 160
+; nextln: brasl %r14, %g
+; nextln: lmg %r14, %r15, 272(%r15)
+; nextln: br %r14
+
+function %f2(i32) -> i64 {
+    fn0 = %g(i32 uext) -> i64
+
+block0(v0: i32):
+    v1 = call fn0(v0)
+    return v1
+}
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; CALL_INDIRECT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %call_indirect(i64, i64) -> i64 {
+    sig0 = (i64) -> i64
+block0(v0: i64, v1: i64):
+    v2 = call_indirect.i64 sig0, v1(v0)
+    return v2
+}
+
+; check:  stmg %r14, %r15, 112(%r15)
+; nextln: aghi %r15, -160
+; nextln: virtual_sp_offset_adjust 160
+; nextln: basr %r14, %r3
+; nextln: lmg %r14, %r15, 272(%r15)
+; nextln: br %r14

cranelift/filetests/filetests/isa/s390x/condbr.clif

@@ -0,0 +1,62 @@
+test compile
+target s390x
+
+function %f(i64, i64) -> b1 {
+block0(v0: i64, v1: i64):
+  v2 = icmp eq v0, v1
+  return v2
+}
+
+; check:  clgr %r2, %r3
+; nextln: lhi %r2, 0
+; nextln: lochie %r2, 1
+; nextln: br %r14
+
+function %f(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = icmp eq v0, v1
+  brnz v2, block1
+  jump block2
+
+block1:
+  v4 = iconst.i64 1
+  return v4
+
+block2:
+  v5 = iconst.i64 2
+  return v5
+}
+
+; check: Block 0:
+; check:  clgr %r2, %r3
+; nextln: jge label1 ; jg label2
+; check: Block 1:
+; check:  lghi %r2, 1
+; nextln: br %r14
+; check: Block 2:
+; check:  lghi %r2, 2
+; nextln: br %r14
+
+function %f(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = icmp eq v0, v1
+  brnz v2, block1
+  jump block1
+
+block1:
+  v4 = iconst.i64 1
+  return v4
+}
+
+; FIXME: Should optimize away branches
+
+; check: Block 0:
+; check:  clgr %r2, %r3
+; nextln: jge label1 ; jg label2
+; check: Block 1:
+; check:  jg label3
+; check: Block 2:
+; check:  jg label3
+; check: Block 3:
+; check:  lghi %r2, 1
+; nextln: br %r14

cranelift/filetests/filetests/isa/s390x/condops.clif

@@ -0,0 +1,43 @@
+test compile
+target s390x
+
+function %f(i8, i64, i64) -> i64 {
+block0(v0: i8, v1: i64, v2: i64):
+  v3 = iconst.i8 42
+  v4 = icmp eq v0, v3
+  v5 = select.i64 v4, v1, v2
+  return v5
+}
+
+; check:  llcr %r2, %r2
+; nextln: clfi %r2, 42
+; nextln: locgre %r4, %r3
+; nextln: lgr %r2, %r4
+; nextln: br %r14
+
+function %g(b1, i8, i8) -> i8 {
+block0(v0: b1, v1: i8, v2: i8):
+  v3 = select.i8 v0, v1, v2
+  return v3
+}
+
+; FIXME: optimize i8/i16 compares
+
+; check:  llcr %r2, %r2
+; nextln: chi %r2, 0
+; nextln: locrlh %r4, %r3
+; nextln: lr %r2, %r4
+; nextln: br %r14
+
+function %i(i32, i8, i8) -> i8 {
+block0(v0: i32, v1: i8, v2: i8):
+  v3 = iconst.i32 42
+  v4 = icmp.i32 eq v0, v3
+  v5 = select.i8 v4, v1, v2
+  return v5
+}
+
+; check:  clfi %r2, 42
+; nextln: locre %r4, %r3
+; nextln: lr %r2, %r4
+; nextln: br %r14

cranelift/filetests/filetests/isa/s390x/constants.clif

@@ -0,0 +1,113 @@
+test compile
+target s390x
+
+function %f() -> b8 {
+block0:
+  v0 = bconst.b8 true
+  return v0
+}
+
+; check:  lhi %r2, 255
+; nextln: br %r14
+
+function %f() -> b16 {
+block0:
+  v0 = bconst.b16 false
+  return v0
+}
+
+; check:  lhi %r2, 0
+; nextln: br %r14
+
+function %f() -> i64 {
+block0:
+  v0 = iconst.i64 0
+  return v0
+}
+
+; check:  lghi %r2, 0
+; nextln: br %r14
+
+function %f() -> i64 {
+block0:
+  v0 = iconst.i64 0xffff
+  return v0
+}
+
+; check:  lgfi %r2, 65535
+; nextln: br %r14
+
+function %f() -> i64 {
+block0:
+  v0 = iconst.i64 0xffff0000
+  return v0
+}
+
+; check:  llilh %r2, 65535
+; nextln: br %r14
+
+function %f() -> i64 {
+block0:
+  v0 = iconst.i64 0xffff00000000
+  return v0
+}
+
+; check:  llihl %r2, 65535
+; nextln: br %r14
+
+function %f() -> i64 {
+block0:
+  v0 = iconst.i64 0xffff000000000000
+  return v0
+}
+
+; check:  llihh %r2, 65535
+; nextln: br %r14
+
+function %f() -> i64 {
+block0:
+  v0 = iconst.i64 0xffffffffffffffff
+  return v0
+}
+
+; check:  lghi %r2, -1
+; nextln: br %r14
+
+function %f() -> i64 {
+block0:
+  v0 = iconst.i64 0xffffffffffff0000
+  return v0
+}
+
+; check:  lgfi %r2, -65536
+; nextln: br %r14
+
+function %f() -> i64 {
+block0:
+  v0 = iconst.i64 0xf34bf0a31212003a ; random digits
+  return v0
+}
+
+; check:  llihf %r2, 4081840291
+; nextln: iilf %r2, 303169594
+; nextln: br %r14
+
+function %f() -> i64 {
+block0:
+  v0 = iconst.i64 0x12e900001ef40000 ; random digits with 2 clear half words
+  return v0
+}
+
+; check:  llihh %r2, 4841
+; nextln: iilh %r2, 7924
+; nextln: br %r14
+
+function %f() -> i32 {
+block0:
+  v0 = iconst.i32 -1
+  return v0
+}
+
+; check:  lhi %r2, -1
+; nextln: br %r14
+

cranelift/filetests/filetests/isa/s390x/conversions.clif

@@ -0,0 +1,748 @@
+test compile
+target s390x
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; UEXTEND
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %uextend_i32_i64(i32) -> i64 {
+block0(v0: i32):
+  v1 = uextend.i64 v0
+  return v1
+}
+
+; check:  llgfr %r2, %r2
+; nextln: br %r14
+
+function %uextend_i16_i64(i16) -> i64 {
+block0(v0: i16):
+  v1 = uextend.i64 v0
+  return v1
+}
+
+; check:  llghr %r2, %r2
+; nextln: br %r14
+
+function %uextend_i16_i32(i16) -> i32 {
+block0(v0: i16):
+  v1 = uextend.i32 v0
+  return v1
+}
+
+; check:  llhr %r2, %r2
+; nextln: br %r14
+
+function %uextend_i8_i64(i8) -> i64 {
+block0(v0: i8):
+  v1 = uextend.i64 v0
+  return v1
+}
+
+; check:  llgcr %r2, %r2
+; nextln: br %r14
+
+function %uextend_i8_i32(i8) -> i32 {
+block0(v0: i8):
+  v1 = uextend.i32 v0
+  return v1
+}
+
+; check:  llcr %r2, %r2
+; nextln: br %r14
+
+function %uextend_i8_i16(i8) -> i16 {
+block0(v0: i8):
+  v1 = uextend.i16 v0
+  return v1
+}
+
+; check:  llcr %r2, %r2
+; nextln: br %r14
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; SEXTEND
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %sextend_i32_i64(i32) -> i64 {
+block0(v0: i32):
+  v1 = sextend.i64 v0
+  return v1
+}
+
+; check:  lgfr %r2, %r2
+; nextln: br %r14
+
+function %sextend_i16_i64(i16) -> i64 {
+block0(v0: i16):
+  v1 = sextend.i64 v0
+  return v1
+}
+
+; check:  lghr %r2, %r2
+; nextln: br %r14
+
+function %sextend_i16_i32(i16) -> i32 {
+block0(v0: i16):
+  v1 = sextend.i32 v0
+  return v1
+}
+
+; check:  lhr %r2, %r2
+; nextln: br %r14
+
+function %sextend_i8_i64(i8) -> i64 {
+block0(v0: i8):
+  v1 = sextend.i64 v0
+  return v1
+}
+
+; check:  lgbr %r2, %r2
+; nextln: br %r14
+
+function %sextend_i8_i32(i8) -> i32 {
+block0(v0: i8):
+  v1 = sextend.i32 v0
+  return v1
+}
+
+; check:  lbr %r2, %r2
+; nextln: br %r14
+
+function %sextend_i8_i16(i8) -> i16 {
+block0(v0: i8):
+  v1 = sextend.i16 v0
+  return v1
+}
+
+; check:  lbr %r2, %r2
+; nextln: br %r14
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; IREDUCE
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %ireduce_i64_i32(i64, i64) -> i32 {
+block0(v0: i64, v1: i64):
+  v2 = ireduce.i32 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %ireduce_i64_i16(i64, i64) -> i16 {
+block0(v0: i64, v1: i64):
+  v2 = ireduce.i16 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %ireduce_i64_i8(i64, i64) -> i8 {
+block0(v0: i64, v1: i64):
+  v2 = ireduce.i8 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %ireduce_i32_i16(i32, i32) -> i16 {
+block0(v0: i32, v1: i32):
+  v2 = ireduce.i16 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %ireduce_i32_i8(i32, i32) -> i8 {
+block0(v0: i32, v1: i32):
+  v2 = ireduce.i8 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %ireduce_i16_i8(i16, i16) -> i8 {
+block0(v0: i16, v1: i16):
+  v2 = ireduce.i8 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; BEXTEND
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %bextend_b32_b64(b32) -> b64 {
+block0(v0: b32):
+  v1 = bextend.b64 v0
+  return v1
+}
+
+; check:  lgfr %r2, %r2
+; nextln: br %r14
+
+function %bextend_b16_b64(b16) -> b64 {
+block0(v0: b16):
+  v1 = bextend.b64 v0
+  return v1
+}
+
+; check:  lghr %r2, %r2
+; nextln: br %r14
+
+function %bextend_b16_b32(b16) -> b32 {
+block0(v0: b16):
+  v1 = bextend.b32 v0
+  return v1
+}
+
+; check:  lhr %r2, %r2
+; nextln: br %r14
+
+function %bextend_b8_b64(b8) -> b64 {
+block0(v0: b8):
+  v1 = bextend.b64 v0
+  return v1
+}
+
+; check:  lgbr %r2, %r2
+; nextln: br %r14
+
+function %bextend_b8_b32(b8) -> b32 {
+block0(v0: b8):
+  v1 = bextend.b32 v0
+  return v1
+}
+
+; check:  lbr %r2, %r2
+; nextln: br %r14
+
+function %bextend_b8_b16(b8) -> b16 {
+block0(v0: b8):
+  v1 = bextend.b16 v0
+  return v1
+}
+
+; check:  lbr %r2, %r2
+; nextln: br %r14
+
+function %bextend_b1_b64(b1) -> b64 {
+block0(v0: b1):
+  v1 = bextend.b64 v0
+  return v1
+}
+
+; check:  sllg %r2, %r2, 63
+; nextln: srag %r2, %r2, 63
+; nextln: br %r14
+
+function %bextend_b1_b32(b1) -> b32 {
+block0(v0: b1):
+  v1 = bextend.b32 v0
+  return v1
+}
+
+; check:  sllk %r2, %r2, 31
+; nextln: srak %r2, %r2, 31
+; nextln: br %r14
+
+function %bextend_b1_b16(b1) -> b16 {
+block0(v0: b1):
+  v1 = bextend.b16 v0
+  return v1
+}
+
+; check:  sllk %r2, %r2, 31
+; nextln: srak %r2, %r2, 31
+; nextln: br %r14
+
+function %bextend_b1_b8(b1) -> b8 {
+block0(v0: b1):
+  v1 = bextend.b8 v0
+  return v1
+}
+
+; check:  sllk %r2, %r2, 31
+; nextln: srak %r2, %r2, 31
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; BREDUCE
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %breduce_b64_b32(b64, b64) -> b32 {
+block0(v0: b64, v1: b64):
+  v2 = breduce.b32 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %breduce_b64_b16(b64, b64) -> b16 {
+block0(v0: b64, v1: b64):
+  v2 = breduce.b16 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %breduce_b64_b8(b64, b64) -> b8 {
+block0(v0: b64, v1: b64):
+  v2 = breduce.b8 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %breduce_b64_b1(b64, b64) -> b1 {
+block0(v0: b64, v1: b64):
+  v2 = breduce.b1 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %breduce_b32_b16(b32, b32) -> b16 {
+block0(v0: b32, v1: b32):
+  v2 = breduce.b16 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %breduce_b32_b8(b32, b32) -> b8 {
+block0(v0: b32, v1: b32):
+  v2 = breduce.b8 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %breduce_b32_b1(b32, b32) -> b1 {
+block0(v0: b32, v1: b32):
+  v2 = breduce.b1 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %breduce_b16_b8(b16, b16) -> b8 {
+block0(v0: b16, v1: b16):
+  v2 = breduce.b8 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %breduce_b16_b1(b16, b16) -> b1 {
+block0(v0: b16, v1: b16):
+  v2 = breduce.b1 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %breduce_b8_b1(b8, b8) -> b1 {
+block0(v0: b8, v1: b8):
+  v2 = breduce.b1 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; BMASK
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %bmask_b64_i64(b64, b64) -> i64 {
+block0(v0: b64, v1: b64):
+  v2 = bmask.i64 v1
+  return v2
+}
+
+; check:  lgr %r2, %r3
+; nextln: br %r14
+
+function %bmask_b64_i32(b64, b64) -> i32 {
+block0(v0: b64, v1: b64):
+  v2 = bmask.i32 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %bmask_b64_i16(b64, b64) -> i16 {
+block0(v0: b64, v1: b64):
+  v2 = bmask.i16 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %bmask_b64_i8(b64, b64) -> i8 {
+block0(v0: b64, v1: b64):
+  v2 = bmask.i8 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %bmask_b32_i64(b32, b32) -> i64 {
+block0(v0: b32, v1: b32):
+  v2 = bmask.i64 v1
+  return v2
+}
+
+; check:  lgfr %r2, %r3
+; nextln: br %r14
+
+function %bmask_b32_i32(b32, b32) -> i32 {
+block0(v0: b32, v1: b32):
+  v2 = bmask.i32 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %bmask_b32_i16(b32, b32) -> i16 {
+block0(v0: b32, v1: b32):
+  v2 = bmask.i16 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %bmask_b32_i8(b32, b32) -> i8 {
+block0(v0: b32, v1: b32):
+  v2 = bmask.i8 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %bmask_b16_i64(b16, b16) -> i64 {
+block0(v0: b16, v1: b16):
+  v2 = bmask.i64 v1
+  return v2
+}
+
+; check:  lghr %r2, %r3
+; nextln: br %r14
+
+function %bmask_b16_i32(b16, b16) -> i32 {
+block0(v0: b16, v1: b16):
+  v2 = bmask.i32 v1
+  return v2
+}
+
+; check:  lhr %r2, %r3
+; nextln: br %r14
+
+function %bmask_b16_i16(b16, b16) -> i16 {
+block0(v0: b16, v1: b16):
+  v2 = bmask.i16 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %bmask_b16_i8(b16, b16) -> i8 {
+block0(v0: b16, v1: b16):
+  v2 = bmask.i8 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %bmask_b8_i64(b8, b8) -> i64 {
+block0(v0: b8, v1: b8):
+  v2 = bmask.i64 v1
+  return v2
+}
+
+; check:  lgbr %r2, %r3
+; nextln: br %r14
+
+function %bmask_b8_i32(b8, b8) -> i32 {
+block0(v0: b8, v1: b8):
+  v2 = bmask.i32 v1
+  return v2
+}
+
+; check:  lbr %r2, %r3
+; nextln: br %r14
+
+function %bmask_b8_i16(b8, b8) -> i16 {
+block0(v0: b8, v1: b8):
+  v2 = bmask.i16 v1
+  return v2
+}
+
+; check:  lbr %r2, %r3
+; nextln: br %r14
+
+function %bmask_b8_i8(b8, b8) -> i8 {
+block0(v0: b8, v1: b8):
+  v2 = bmask.i8 v1
+  return v2
+}
+
+; check:  lr %r2, %r3
+; nextln: br %r14
+
+function %bmask_b1_i64(b1, b1) -> i64 {
+block0(v0: b1, v1: b1):
+  v2 = bmask.i64 v1
+  return v2
+}
+
+; check:  sllg %r2, %r3, 63
+; nextln: srag %r2, %r2, 63
+; nextln: br %r14
+
+function %bmask_b1_i32(b1, b1) -> i32 {
+block0(v0: b1, v1: b1):
+  v2 = bmask.i32 v1
+  return v2
+}
+
+; check:  sllk %r2, %r3, 31
+; nextln: srak %r2, %r2, 31
+; nextln: br %r14
+
+function %bmask_b1_i16(b1, b1) -> i16 {
+block0(v0: b1, v1: b1):
+  v2 = bmask.i16 v1
+  return v2
+}
+
+; check:  sllk %r2, %r3, 31
+; nextln: srak %r2, %r2, 31
+; nextln: br %r14
+
+function %bmask_b1_i8(b1, b1) -> i8 {
+block0(v0: b1, v1: b1):
+  v2 = bmask.i8 v1
+  return v2
+}
+
+; check:  sllk %r2, %r3, 31
+; nextln: srak %r2, %r2, 31
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; BINT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %bint_b64_i64(b64) -> i64 {
+block0(v0: b64):
+  v1 = bint.i64 v0
+  return v1
+}
+
+; check:  lghi %r3, 1
+; nextln: ngr %r2, %r3
+; nextln: br %r14
+
+function %bint_b64_i32(b64) -> i32 {
+block0(v0: b64):
+  v1 = bint.i32 v0
+  return v1
+}
+
+; check:  nilf %r2, 1
+; nextln: br %r14
+
+function %bint_b64_i16(b64) -> i16 {
+block0(v0: b64):
+  v1 = bint.i16 v0
+  return v1
+}
+
+; check:  nill %r2, 1
+; nextln: br %r14
+
+function %bint_b64_i8(b64) -> i8 {
+block0(v0: b64):
+  v1 = bint.i8 v0
+  return v1
+}
+
+; check:  nill %r2, 1
+; nextln: br %r14
+
+function %bint_b32_i64(b32) -> i64 {
+block0(v0: b32):
+  v1 = bint.i64 v0
+  return v1
+}
+
+; check:  lghi %r3, 1
+; nextln: ngr %r2, %r3
+; nextln: br %r14
+
+function %bint_b32_i32(b32) -> i32 {
+block0(v0: b32):
+  v1 = bint.i32 v0
+  return v1
+}
+
+; check:  nilf %r2, 1
+; nextln: br %r14
+
+function %bint_b32_i16(b32) -> i16 {
+block0(v0: b32):
+  v1 = bint.i16 v0
+  return v1
+}
+
+; check:  nill %r2, 1
+; nextln: br %r14
+
+function %bint_b32_i8(b32) -> i8 {
+block0(v0: b32):
+  v1 = bint.i8 v0
+  return v1
+}
+
+; check:  nill %r2, 1
+; nextln: br %r14
+
+function %bint_b16_i64(b16) -> i64 {
+block0(v0: b16):
+  v1 = bint.i64 v0
+  return v1
+}
+
+; check:  lghi %r3, 1
+; nextln: ngr %r2, %r3
+; nextln: br %r14
+
+function %bint_b16_i32(b16) -> i32 {
+block0(v0: b16):
+  v1 = bint.i32 v0
+  return v1
+}
+
+; check:  nilf %r2, 1
+; nextln: br %r14
+
+function %bint_b16_i16(b16) -> i16 {
+block0(v0: b16):
+  v1 = bint.i16 v0
+  return v1
+}
+
+; check:  nill %r2, 1
+; nextln: br %r14
+
+function %bint_b16_i8(b16) -> i8 {
+block0(v0: b16):
+  v1 = bint.i8 v0
+  return v1
+}
+
+; check:  nill %r2, 1
+; nextln: br %r14
+
+function %bint_b8_i64(b8) -> i64 {
+block0(v0: b8):
+  v1 = bint.i64 v0
+  return v1
+}
+
+; check:  lghi %r3, 1
+; nextln: ngr %r2, %r3
+; nextln: br %r14
+
+function %bint_b8_i32(b8) -> i32 {
+block0(v0: b8):
+  v1 = bint.i32 v0
+  return v1
+}
+
+; check:  nilf %r2, 1
+; nextln: br %r14
+
+function %bint_b8_i16(b8) -> i16 {
+block0(v0: b8):
+  v1 = bint.i16 v0
+  return v1
+}
+
+; check:  nill %r2, 1
+; nextln: br %r14
+
+function %bint_b8_i8(b8) -> i8 {
+block0(v0: b8):
+  v1 = bint.i8 v0
+  return v1
+}
+
+; check:  nill %r2, 1
+; nextln: br %r14
+
+function %bint_b1_i64(b1) -> i64 {
+block0(v0: b1):
+  v1 = bint.i64 v0
+  return v1
+}
+
+; check:  lghi %r3, 1
+; nextln: ngr %r2, %r3
+; nextln: br %r14
+
+function %bint_b1_i32(b1) -> i32 {
+block0(v0: b1):
+  v1 = bint.i32 v0
+  return v1
+}
+
+; check:  nilf %r2, 1
+; nextln: br %r14
+
+function %bint_b1_i16(b1) -> i16 {
+block0(v0: b1):
+  v1 = bint.i16 v0
+  return v1
+}
+
+; check:  nill %r2, 1
+; nextln: br %r14
+
+function %bint_b1_i8(b1) -> i8 {
+block0(v0: b1):
+  v1 = bint.i8 v0
+  return v1
+}
+
+; check:  nill %r2, 1
+; nextln: br %r14
+

cranelift/filetests/filetests/isa/s390x/div-traps.clif

@@ -0,0 +1,355 @@
+test compile
+set avoid_div_traps=1
+target s390x
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; SDIV
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %sdiv_i64(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = sdiv.i64 v0, v1
+  return v2
+}
+
+; check:  lgr %r1, %r2
+; nextln: cgite %r3, 0
+; nextln: llihf %r2, 2147483647
+; nextln: iilf %r2, 4294967295
+; nextln: xgr %r2, %r1
+; nextln: ngr %r2, %r3
+; nextln: cgite %r2, -1
+; nextln: dsgr %r0, %r3
+; nextln: lgr %r2, %r1
+; nextln: br %r14
+
+function %sdiv_i64_imm(i64) -> i64 {
+block0(v0: i64):
+  v1 = iconst.i64 2
+  v2 = sdiv.i64 v0, v1
+  return v2
+}
+
+; check:  lgr %r1, %r2
+; nextln: lghi %r2, 2
+; nextln: dsgr %r0, %r2
+; nextln: lgr %r2, %r1
+; nextln: br %r14
+
+function %sdiv_i32(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = sdiv.i32 v0, v1
+  return v2
+}
+
+; check:  lgfr %r1, %r2
+; nextln: cite %r3, 0
+; nextln: iilf %r2, 2147483647
+; nextln: xr %r2, %r1
+; nextln: nr %r2, %r3
+; nextln: cite %r2, -1
+; nextln: dsgfr %r0, %r3
+; nextln: lr %r2, %r1
+; nextln: br %r14
+
+function %sdiv_i32_imm(i32) -> i32 {
+block0(v0: i32):
+  v1 = iconst.i32 2
+  v2 = sdiv.i32 v0, v1
+  return v2
+}
+
+; check:  lgfr %r1, %r2
+; nextln: lhi %r2, 2
+; nextln: dsgfr %r0, %r2
+; nextln: lr %r2, %r1
+; nextln: br %r14
+
+function %sdiv_i16(i16, i16) -> i16 {
+block0(v0: i16, v1: i16):
+  v2 = sdiv.i16 v0, v1
+  return v2
+}
+
+; check:  lghr %r1, %r2
+; nextln: lhr %r2, %r3
+; nextln: cite %r2, 0
+; nextln: lhi %r3, 32767
+; nextln: xr %r3, %r1
+; nextln: nr %r3, %r2
+; nextln: cite %r3, -1
+; nextln: dsgfr %r0, %r2
+; nextln: lr %r2, %r1
+; nextln: br %r14
+
+function %sdiv_i16_imm(i16) -> i16 {
+block0(v0: i16):
+  v1 = iconst.i16 2
+  v2 = sdiv.i16 v0, v1
+  return v2
+}
+
+; check:  lghr %r1, %r2
+; nextln: lhi %r2, 2
+; nextln: dsgfr %r0, %r2
+; nextln: lr %r2, %r1
+; nextln: br %r14
+
+function %sdiv_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+  v2 = sdiv.i8 v0, v1
+  return v2
+}
+
+; check:  lgbr %r1, %r2
+; nextln: lbr %r2, %r3
+; nextln: cite %r2, 0
+; nextln: lhi %r3, 127
+; nextln: xr %r3, %r1
+; nextln: nr %r3, %r2
+; nextln: cite %r3, -1
+; nextln: dsgfr %r0, %r2
+; nextln: lr %r2, %r1
+; nextln: br %r14
+
+function %sdiv_i8_imm(i8) -> i8 {
+block0(v0: i8):
+  v1 = iconst.i8 2
+  v2 = sdiv.i8 v0, v1
+  return v2
+}
+
+; check:  lgbr %r1, %r2
+; nextln: lhi %r2, 2
+; nextln: dsgfr %r0, %r2
+; nextln: lr %r2, %r1
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; UDIV
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %udiv_i64(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = udiv.i64 v0, v1
+  return v2
+}
+
+; check:  lghi %r0, 0
+; nextln: lgr %r1, %r2
+; nextln: cgite %r3, 0
+; nextln: dlgr %r0, %r3
+; nextln: lgr %r2, %r1
+; nextln: br %r14
+
+function %udiv_i64_imm(i64) -> i64 {
+block0(v0: i64):
+  v1 = iconst.i64 2
+  v2 = udiv.i64 v0, v1
+  return v2
+}
+
+; check:  lghi %r0, 0
+; nextln: lgr %r1, %r2
+; nextln: lghi %r2, 2
+; nextln: dlgr %r0, %r2
+; nextln: lgr %r2, %r1
+; nextln: br %r14
+
+function %udiv_i32(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = udiv.i32 v0, v1
+  return v2
+}
+
+; check:  lhi %r0, 0
+; nextln: lr %r1, %r2
+; nextln: cite %r3, 0
+; nextln: dlr %r0, %r3
+; nextln: lr %r2, %r1
+; nextln: br %r14
+
+function %udiv_i32_imm(i32) -> i32 {
+block0(v0: i32):
+  v1 = iconst.i32 2
+  v2 = udiv.i32 v0, v1
+  return v2
+}
+
+; check:  lhi %r0, 0
+; nextln: lr %r1, %r2
+; nextln: lhi %r2, 2
+; nextln: dlr %r0, %r2
+; nextln: lr %r2, %r1
+; nextln: br %r14
+
+function %udiv_i16(i16, i16) -> i16 {
+block0(v0: i16, v1: i16):
+  v2 = udiv.i16 v0, v1
+  return v2
+}
+
+; check:  lhi %r0, 0
+; nextln: llhr %r1, %r2
+; nextln: llhr %r2, %r3
+; nextln: cite %r2, 0
+; nextln: dlr %r0, %r2
+; nextln: lr %r2, %r1
+; nextln: br %r14
+
+function %udiv_i16_imm(i16) -> i16 {
+block0(v0: i16):
+  v1 = iconst.i16 2
+  v2 = udiv.i16 v0, v1
+  return v2
+}
+
+; check:  lhi %r0, 0
+; nextln: llhr %r1, %r2
+; nextln: lhi %r2, 2
+; nextln: dlr %r0, %r2
+; nextln: lr %r2, %r1
+; nextln: br %r14
+
+function %udiv_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+  v2 = udiv.i8 v0, v1
+  return v2
+}
+
+; check:  lhi %r0, 0
+; nextln: llcr %r1, %r2
+; nextln: llcr %r2, %r3
+; nextln: cite %r2, 0
+; nextln: dlr %r0, %r2
+; nextln: lr %r2, %r1
+; nextln: br %r14
+
+function %udiv_i8_imm(i8) -> i8 {
+block0(v0: i8):
+  v1 = iconst.i8 2
+  v2 = udiv.i8 v0, v1
+  return v2
+}
+
+; check:  lhi %r0, 0
+; nextln: llcr %r1, %r2
+; nextln: lhi %r2, 2
+; nextln: dlr %r0, %r2
+; nextln: lr %r2, %r1
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; SREM
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %srem_i64(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = srem.i64 v0, v1
+  return v2
+}
+
+; check:  lgr %r1, %r2
+; nextln: cgite %r3, 0
+; nextln: cghi %r3, -1
+; nextln: locghie %r1, 0
+; nextln: dsgr %r0, %r3
+; nextln: lgr %r2, %r0
+; nextln: br %r14
+
+function %srem_i32(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = srem.i32 v0, v1
+  return v2
+}
+
+; check:  lgfr %r1, %r2
+; nextln: cite %r3, 0
+; nextln: dsgfr %r0, %r3
+; nextln: lr %r2, %r0
+; nextln: br %r14
+
+function %srem_i16(i16, i16) -> i16 {
+block0(v0: i16, v1: i16):
+  v2 = srem.i16 v0, v1
+  return v2
+}
+
+; check:  lghr %r1, %r2
+; nextln: lhr %r2, %r3
+; nextln: cite %r2, 0
+; nextln: dsgfr %r0, %r2
+; nextln: lr %r2, %r0
+; nextln: br %r14
+
+function %srem_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+  v2 = srem.i8 v0, v1
+  return v2
+}
+
+; check:  lgbr %r1, %r2
+; nextln: lbr %r2, %r3
+; nextln: cite %r2, 0
+; nextln: dsgfr %r0, %r2
+; nextln: lr %r2, %r0
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; UREM
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %urem_i64(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = urem.i64 v0, v1
+  return v2
+}
+
+; check:  lghi %r0, 0
+; nextln: lgr %r1, %r2
+; nextln: cgite %r3, 0
+; nextln: dlgr %r0, %r3
+; nextln: lgr %r2, %r0
+; nextln: br %r14
+
+function %urem_i32(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = urem.i32 v0, v1
+  return v2
+}
+
+; check:  lhi %r0, 0
+; nextln: lr %r1, %r2
+; nextln: cite %r3, 0
+; nextln: dlr %r0, %r3
+; nextln: lr %r2, %r0
+; nextln: br %r14
+
+function %urem_i16(i16, i16) -> i16 {
+block0(v0: i16, v1: i16):
+  v2 = urem.i16 v0, v1
+  return v2
+}
+
+; check:  lhi %r0, 0
+; nextln: llhr %r1, %r2
+; nextln: llhr %r2, %r3
+; nextln: cite %r2, 0
+; nextln: dlr %r0, %r2
+; nextln: lr %r2, %r0
+; nextln: br %r14
+
+function %urem_i8(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+  v2 = urem.i8 v0, v1
+  return v2
+}
+
+; check:  lhi %r0, 0
+; nextln: llcr %r1, %r2
+; nextln: llcr %r2, %r3
+; nextln: cite %r2, 0
+; nextln: dlr %r0, %r2
+; nextln: lr %r2, %r0
+; nextln: br %r14
+

cranelift/filetests/filetests/isa/s390x/floating-point.clif

@@ -0,0 +1,711 @@
+test compile
+target s390x
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; F32CONST/F64CONST
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; FIXME: should use FZERO instruction
+; FIXME: should use out-of-line literal pool
+
+function %f32const_zero() -> f32 {
+block0:
+  v1 = f32const 0x0.0
+  return v1
+}
+
+; check:  bras %r1, 8 ; data.f32 0 ; le %f0, 0(%r1)
+; nextln: br %r14
+
+function %f64const_zero() -> f64 {
+block0:
+  v1 = f64const 0x0.0
+  return v1
+}
+
+; check:  bras %r1, 12 ; data.f64 0 ; ld %f0, 0(%r1)
+; nextln: br %r14
+
+function %f32const_one() -> f32 {
+block0:
+  v1 = f32const 0x1.0
+  return v1
+}
+
+; check:  bras %r1, 8 ; data.f32 1 ; le %f0, 0(%r1)
+; nextln: br %r14
+
+function %f64const_one() -> f64 {
+block0:
+  v1 = f64const 0x1.0
+  return v1
+}
+
+; check:  bras %r1, 12 ; data.f64 1 ; ld %f0, 0(%r1)
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; FADD
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %fadd_f32(f32, f32) -> f32 {
+block0(v0: f32, v1: f32):
+  v2 = fadd v0, v1
+  return v2
+}
+
+; check:  aebr %f0, %f2
+; nextln: br %r14
+
+function %fadd_f64(f64, f64) -> f64 {
+block0(v0: f64, v1: f64):
+  v2 = fadd v0, v1
+  return v2
+}
+
+; check:  adbr %f0, %f2
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; FSUB
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %fsub_f32(f32, f32) -> f32 {
+block0(v0: f32, v1: f32):
+  v2 = fsub v0, v1
+  return v2
+}
+
+; check:  sebr %f0, %f2
+; nextln: br %r14
+
+function %fsub_f64(f64, f64) -> f64 {
+block0(v0: f64, v1: f64):
+  v2 = fsub v0, v1
+  return v2
+}
+
+; check:  sdbr %f0, %f2
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; FMUL
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %fmul_f32(f32, f32) -> f32 {
+block0(v0: f32, v1: f32):
+  v2 = fmul v0, v1
+  return v2
+}
+
+; check:  meebr %f0, %f2
+; nextln: br %r14
+
+function %fmul_f64(f64, f64) -> f64 {
+block0(v0: f64, v1: f64):
+  v2 = fmul v0, v1
+  return v2
+}
+
+; check:  mdbr %f0, %f2
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; FDIV
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %fdiv_f32(f32, f32) -> f32 {
+block0(v0: f32, v1: f32):
+  v2 = fdiv v0, v1
+  return v2
+}
+
+; check:  debr %f0, %f2
+; nextln: br %r14
+
+function %fdiv_f64(f64, f64) -> f64 {
+block0(v0: f64, v1: f64):
+  v2 = fdiv v0, v1
+  return v2
+}
+
+; check:  ddbr %f0, %f2
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; FMIN
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %fmin_f32(f32, f32) -> f32 {
+block0(v0: f32, v1: f32):
+  v2 = fmin v0, v1
+  return v2
+}
+
+; check:  wfminsb %f0, %f0, %f2, 1
+; nextln: br %r14
+
+function %fmin_f64(f64, f64) -> f64 {
+block0(v0: f64, v1: f64):
+  v2 = fmin v0, v1
+  return v2
+}
+
+; check:  wfmindb %f0, %f0, %f2, 1
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; FMAX
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %fmax_f32(f32, f32) -> f32 {
+block0(v0: f32, v1: f32):
+  v2 = fmax v0, v1
+  return v2
+}
+
+; check:  wfmaxsb %f0, %f0, %f2, 1
+; nextln: br %r14
+
+function %fmax_f64(f64, f64) -> f64 {
+block0(v0: f64, v1: f64):
+  v2 = fmax v0, v1
+  return v2
+}
+
+; check:  wfmaxdb %f0, %f0, %f2, 1
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; SQRT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %sqrt_f32(f32) -> f32 {
+block0(v0: f32):
+  v1 = sqrt v0
+  return v1
+}
+
+; check:  sqebr %f0, %f0
+; nextln: br %r14
+
+function %sqrt_f64(f64) -> f64 {
+block0(v0: f64):
+  v1 = sqrt v0
+  return v1
+}
+
+; check:  sqdbr %f0, %f0
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; FABS
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %fabs_f32(f32) -> f32 {
+block0(v0: f32):
+  v1 = fabs v0
+  return v1
+}
+
+; check:  lpebr %f0, %f0
+; nextln: br %r14
+
+function %fabs_f64(f64) -> f64 {
+block0(v0: f64):
+  v1 = fabs v0
+  return v1
+}
+
+; check:  lpdbr %f0, %f0
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; FNEG
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %fneg_f32(f32) -> f32 {
+block0(v0: f32):
+  v1 = fneg v0
+  return v1
+}
+
+; check:  lcebr %f0, %f0
+; nextln: br %r14
+
+function %fneg_f64(f64) -> f64 {
+block0(v0: f64):
+  v1 = fneg v0
+  return v1
+}
+
+; check:  lcdbr %f0, %f0
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; FPROMOTE/FDEMOTE
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %fpromote_f32(f32) -> f64 {
+block0(v0: f32):
+  v1 = fpromote.f64 v0
+  return v1
+}
+
+; check:  ldebr %f0, %f0
+; nextln: br %r14
+
+function %fdemote_f64(f64) -> f32 {
+block0(v0: f64):
+  v1 = fdemote.f32 v0
+  return v1
+}
+
+; check:  ledbr %f0, %f0
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; CEIL
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %ceil_f32(f32) -> f32 {
+block0(v0: f32):
+  v1 = ceil v0
+  return v1
+}
+
+; check:  fiebr %f0, %f0, 6
+; nextln: br %r14
+
+function %ceil_f64(f64) -> f64 {
+block0(v0: f64):
+  v1 = ceil v0
+  return v1
+}
+
+; check:  fidbr %f0, %f0, 6
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; FLOOR
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %floor_f32(f32) -> f32 {
+block0(v0: f32):
+  v1 = floor v0
+  return v1
+}
+
+; check:  fiebr %f0, %f0, 7
+; nextln: br %r14
+
+function %floor_f64(f64) -> f64 {
+block0(v0: f64):
+  v1 = floor v0
+  return v1
+}
+
+; check:  fidbr %f0, %f0, 7
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; TRUNC
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %trunc_f32(f32) -> f32 {
+block0(v0: f32):
+  v1 = trunc v0
+  return v1
+}
+
+; check:  fiebr %f0, %f0, 5
+; nextln: br %r14
+
+function %trunc_f64(f64) -> f64 {
+block0(v0: f64):
+  v1 = trunc v0
+  return v1
+}
+
+; check:  fidbr %f0, %f0, 5
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; NEAREST
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %nearest_f32(f32) -> f32 {
+block0(v0: f32):
+  v1 = nearest v0
+  return v1
+}
+
+; check:  fiebr %f0, %f0, 4
+; nextln: br %r14
+
+function %nearest_f64(f64) -> f64 {
+block0(v0: f64):
+  v1 = nearest v0
+  return v1
+}
+
+; check:  fidbr %f0, %f0, 4
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; FMA
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %fma_f32(f32, f32, f32) -> f32 {
+block0(v0: f32, v1: f32, v2: f32):
+  v3 = fma v0, v1, v2
+  return v3
+}
+
+; FIXME: regalloc
+
+; check:  maebr %f4, %f0, %f2
+; nextln: ler %f0, %f4
+; nextln: br %r14
+
+function %fma_f64(f64, f64, f64) -> f64 {
+block0(v0: f64, v1: f64, v2: f64):
+  v3 = fma v0, v1, v2
+  return v3
+}
+
+; check:  madbr %f4, %f0, %f2
+; nextln: ldr %f0, %f4
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; FCOPYSIGN
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %fcopysign_f32(f32, f32) -> f32 {
+block0(v0: f32, v1: f32):
+  v2 = fcopysign v0, v1
+  return v2
+}
+
+; check:  cpsdr %f0, %f2, %f0
+; nextln: br %r14
+
+function %fcopysign_f64(f64, f64) -> f64 {
+block0(v0: f64, v1: f64):
+  v2 = fcopysign v0, v1
+  return v2
+}
+
+; check:  cpsdr %f0, %f2, %f0
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; FCVT_TO_UINT/FCVT_TO_SINT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %fcvt_to_uint_f32_i32(f32) -> i32 {
+block0(v0: f32):
+  v1 = fcvt_to_uint.i32 v0
+  return v1
+}
+
+; check:  cebr %f0, %f0
+; nextln: jno 6 ; trap
+; nextln: clfebr %r2, 5, %f0, 0
+; nextln: jno 6 ; trap
+; nextln: br %r14
+
+function %fcvt_to_sint_f32_i32(f32) -> i32 {
+block0(v0: f32):
+  v1 = fcvt_to_sint.i32 v0
+  return v1
+}
+
+; check:  cebr %f0, %f0
+; nextln: jno 6 ; trap
+; nextln: cfebra %r2, 5, %f0, 0
+; nextln: jno 6 ; trap
+; nextln: br %r14
+
+function %fcvt_to_uint_f32_i64(f32) -> i64 {
+block0(v0: f32):
+  v1 = fcvt_to_uint.i64 v0
+  return v1
+}
+
+; check:  cebr %f0, %f0
+; nextln: jno 6 ; trap
+; nextln: clgebr %r2, 5, %f0, 0
+; nextln: jno 6 ; trap
+; nextln: br %r14
+
+function %fcvt_to_sint_f32_i64(f32) -> i64 {
+block0(v0: f32):
+  v1 = fcvt_to_sint.i64 v0
+  return v1
+}
+
+; check:  cebr %f0, %f0
+; nextln: jno 6 ; trap
+; nextln: cgebra %r2, 5, %f0, 0
+; nextln: jno 6 ; trap
+; nextln: br %r14
+
+function %fcvt_to_uint_f64_i32(f64) -> i32 {
+block0(v0: f64):
+  v1 = fcvt_to_uint.i32 v0
+  return v1
+}
+
+; check:  cdbr %f0, %f0
+; nextln: jno 6 ; trap
+; nextln: clfdbr %r2, 5, %f0, 0
+; nextln: jno 6 ; trap
+; nextln: br %r14
+
+function %fcvt_to_sint_f64_i32(f64) -> i32 {
+block0(v0: f64):
+  v1 = fcvt_to_sint.i32 v0
+  return v1
+}
+
+; check:  cdbr %f0, %f0
+; nextln: jno 6 ; trap
+; nextln: cfdbra %r2, 5, %f0, 0
+; nextln: jno 6 ; trap
+; nextln: br %r14
+
+function %fcvt_to_uint_f64_i64(f64) -> i64 {
+block0(v0: f64):
+  v1 = fcvt_to_uint.i64 v0
+  return v1
+}
+
+; check:  cdbr %f0, %f0
+; nextln: jno 6 ; trap
+; nextln: clgdbr %r2, 5, %f0, 0
+; nextln: jno 6 ; trap
+; nextln: br %r14
+
+function %fcvt_to_sint_f64_i64(f64) -> i64 {
+block0(v0: f64):
+  v1 = fcvt_to_sint.i64 v0
+  return v1
+}
+
+; check:  cdbr %f0, %f0
+; nextln: jno 6 ; trap
+; nextln: cgdbra %r2, 5, %f0, 0
+; nextln: jno 6 ; trap
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; FCVT_FROM_UINT/FCVT_FROM_SINT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %fcvt_from_uint_i32_f32(i32) -> f32 {
+block0(v0: i32):
+  v1 = fcvt_from_uint.f32 v0
+  return v1
+}
+
+; check:  celfbr %f0, 0, %r2, 0
+; nextln: br %r14
+
+function %fcvt_from_sint_i32_f32(i32) -> f32 {
+block0(v0: i32):
+  v1 = fcvt_from_sint.f32 v0
+  return v1
+}
+
+; check:  cefbra %f0, 0, %r2, 0
+; nextln: br %r14
+
+function %fcvt_from_uint_i64_f32(i64) -> f32 {
+block0(v0: i64):
+  v1 = fcvt_from_uint.f32 v0
+  return v1
+}
+
+; check:  celgbr %f0, 0, %r2, 0
+; nextln: br %r14
+
+function %fcvt_from_sint_i64_f32(i64) -> f32 {
+block0(v0: i64):
+  v1 = fcvt_from_sint.f32 v0
+  return v1
+}
+
+; check:  cegbra %f0, 0, %r2, 0
+; nextln: br %r14
+
+function %fcvt_from_uint_i32_f64(i32) -> f64 {
+block0(v0: i32):
+  v1 = fcvt_from_uint.f64 v0
+  return v1
+}
+
+; check:  cdlfbr %f0, 0, %r2, 0
+; nextln: br %r14
+
+function %fcvt_from_sint_i32_f64(i32) -> f64 {
+block0(v0: i32):
+  v1 = fcvt_from_sint.f64 v0
+  return v1
+}
+
+; check:  cdfbra %f0, 0, %r2, 0
+; nextln: br %r14
+
+function %fcvt_from_uint_i64_f64(i64) -> f64 {
+block0(v0: i64):
+  v1 = fcvt_from_uint.f64 v0
+  return v1
+}
+
+; check:  cdlgbr %f0, 0, %r2, 0
+; nextln: br %r14
+
+function %fcvt_from_sint_i64_f64(i64) -> f64 {
+block0(v0: i64):
+  v1 = fcvt_from_sint.f64 v0
+  return v1
+}
+
+; check:  cdgbra %f0, 0, %r2, 0
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; FCVT_TO_UINT_SAT/FCVT_TO_SINT_SAT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %fcvt_to_uint_sat_f32_i32(f32) -> i32 {
+block0(v0: f32):
+  v1 = fcvt_to_uint_sat.i32 v0
+  return v1
+}
+
+; check:  clfebr %r2, 5, %f0, 0
+; nextln: cebr %f0, %f0
+; nextln: lochio %r2, 0
+; nextln: br %r14
+
+function %fcvt_to_sint_sat_f32_i32(f32) -> i32 {
+block0(v0: f32):
+  v1 = fcvt_to_sint_sat.i32 v0
+  return v1
+}
+
+; check:  cfebra %r2, 5, %f0, 0
+; nextln: cebr %f0, %f0
+; nextln: lochio %r2, 0
+; nextln: br %r14
+
+function %fcvt_to_uint_sat_f32_i64(f32) -> i64 {
+block0(v0: f32):
+  v1 = fcvt_to_uint_sat.i64 v0
+  return v1
+}
+
+; check:  clgebr %r2, 5, %f0, 0
+; nextln: cebr %f0, %f0
+; nextln: locghio %r2, 0
+; nextln: br %r14
+
+function %fcvt_to_sint_sat_f32_i64(f32) -> i64 {
+block0(v0: f32):
+  v1 = fcvt_to_sint_sat.i64 v0
+  return v1
+}
+
+; check:  cgebra %r2, 5, %f0, 0
+; nextln: cebr %f0, %f0
+; nextln: locghio %r2, 0
+; nextln: br %r14
+
+function %fcvt_to_uint_sat_f64_i32(f64) -> i32 {
+block0(v0: f64):
+  v1 = fcvt_to_uint_sat.i32 v0
+  return v1
+}
+
+; check:  clfdbr %r2, 5, %f0, 0
+; nextln: cdbr %f0, %f0
+; nextln: lochio %r2, 0
+; nextln: br %r14
+
+function %fcvt_to_sint_sat_f64_i32(f64) -> i32 {
+block0(v0: f64):
+  v1 = fcvt_to_sint_sat.i32 v0
+  return v1
+}
+
+; check:  cfdbra %r2, 5, %f0, 0
+; nextln: cdbr %f0, %f0
+; nextln: lochio %r2, 0
+; nextln: br %r14
+
+function %fcvt_to_uint_sat_f64_i64(f64) -> i64 {
+block0(v0: f64):
+  v1 = fcvt_to_uint_sat.i64 v0
+  return v1
+}
+
+; check:  clgdbr %r2, 5, %f0, 0
+; nextln: cdbr %f0, %f0
+; nextln: locghio %r2, 0
+; nextln: br %r14
+
+function %fcvt_to_sint_sat_f64_i64(f64) -> i64 {
+block0(v0: f64):
+  v1 = fcvt_to_sint_sat.i64 v0
+  return v1
+}
+
+; check:  cgdbra %r2, 5, %f0, 0
+; nextln: cdbr %f0, %f0
+; nextln: locghio %r2, 0
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; BITCAST
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %bitcast_i64_f64(i64) -> f64 {
+block0(v0: i64):
+  v1 = bitcast.f64 v0
+  return v1
+}
+
+; check:  ldgr %f0, %r2
+; nextln: br %r14
+
+function %bitcast_f64_i64(f64) -> i64 {
+block0(v0: f64):
+  v1 = bitcast.i64 v0
+  return v1
+}
+
+; check:  lgdr %r2, %f0
+; nextln: br %r14
+
+function %bitcast_i32_f32(i32) -> f32 {
+block0(v0: i32):
+  v1 = bitcast.f32 v0
+  return v1
+}
+
+; check:  sllg %r2, %r2, 32
+; nextln: ldgr %f0, %r2
+; nextln: br %r14
+
+function %bitcast_f32_i32(f32) -> i32 {
+block0(v0: f32):
+  v1 = bitcast.i32 v0
+  return v1
+}
+
+; check:  lgdr %r2, %f0
+; nextln: srlg %r2, %r2, 32
+; nextln: br %r14

cranelift/filetests/filetests/isa/s390x/heap_addr.clif

@@ -0,0 +1,49 @@
+test compile
+target s390x
+
+function %dynamic_heap_check(i64 vmctx, i32) -> i64 {
+    gv0 = vmctx
+    gv1 = load.i32 notrap aligned gv0
+    heap0 = dynamic gv0, bound gv1, offset_guard 0x1000, index_type i32
+
+block0(v0: i64, v1: i32):
+    v2 = heap_addr.i64 heap0, v1, 0
+    return v2
+}
+
+; check: Block 0:
+; check:  l %r4, 0(%r2)
+; nextln: ahi %r4, 0
+; nextln: clr %r3, %r4
+; nextln: jgnh label1 ; jg label2
+; check: Block 1:
+; check:  llgfr %r5, %r3
+; nextln: agr %r2, %r5
+; nextln: lghi %r5, 0
+; nextln: clr %r3, %r4
+; nextln: locgrh %r2, %r5
+; nextln: br %r14
+; check: Block 2:
+; check:  trap
+
+function %static_heap_check(i64 vmctx, i32) -> i64 {
+    gv0 = vmctx
+    heap0 = static gv0, bound 0x1_0000, offset_guard 0x1000, index_type i32
+
+block0(v0: i64, v1: i32):
+    v2 = heap_addr.i64 heap0, v1, 0
+    return v2
+}
+
+; check: Block 0:
+; check:  clfi %r3, 65536
+; nextln: jgnh label1 ; jg label2
+; check: Block 1:
+; check:  llgfr %r4, %r3
+; nextln: agr %r2, %r4
+; nextln: lghi %r4, 0
+; nextln: clfi %r3, 65536
+; nextln: locgrh %r2, %r4
+; nextln: br %r14
+; check: Block 2:
+; check:  trap

cranelift/filetests/filetests/isa/s390x/icmp.clif

@@ -0,0 +1,604 @@
+test compile
+target s390x
+
+function %icmp_slt_i64(i64, i64) -> b1 {
+block0(v0: i64, v1: i64):
+  v2 = icmp.i64 slt v0, v1
+  return v2
+}
+
+; check:  cgr %r2, %r3
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i64_ext32(i64, i32) -> b1 {
+block0(v0: i64, v1: i32):
+  v2 = sextend.i64 v1
+  v3 = icmp.i64 slt v0, v2
+  return v3
+}
+
+; check:  cgfr %r2, %r3
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i64_imm16(i64) -> b1 {
+block0(v0: i64):
+  v1 = iconst.i64 1
+  v2 = icmp.i64 slt v0, v1
+  return v2
+}
+
+; check:  cghi %r2, 1
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i64_imm32(i64) -> b1 {
+block0(v0: i64):
+  v1 = iconst.i64 32768
+  v2 = icmp.i64 slt v0, v1
+  return v2
+}
+
+; check:  cgfi %r2, 32768
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i64_mem(i64, i64) -> b1 {
+block0(v0: i64, v1: i64):
+  v2 = load.i64 v1
+  v3 = icmp.i64 slt v0, v2
+  return v3
+}
+
+; check:  cg %r2, 0(%r3)
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i64_sym(i64) -> b1 {
+  gv0 = symbol colocated %sym
+block0(v0: i64):
+  v1 = symbol_value.i64 gv0
+  v2 = load.i64 v1
+  v3 = icmp.i64 slt v0, v2
+  return v3
+}
+
+; check:  cgrl %r2, %sym + 0
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i64_mem_ext16(i64, i64) -> b1 {
+block0(v0: i64, v1: i64):
+  v2 = sload16.i64 v1
+  v3 = icmp.i64 slt v0, v2
+  return v3
+}
+
+; check:  cgh %r2, 0(%r3)
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i64_sym_ext16(i64) -> b1 {
+  gv0 = symbol colocated %sym
+block0(v0: i64):
+  v1 = symbol_value.i64 gv0
+  v2 = sload16.i64 v1
+  v3 = icmp.i64 slt v0, v2
+  return v3
+}
+
+; check:  cghrl %r2, %sym + 0
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i64_mem_ext32(i64, i64) -> b1 {
+block0(v0: i64, v1: i64):
+  v2 = sload32.i64 v1
+  v3 = icmp.i64 slt v0, v2
+  return v3
+}
+
+; check:  cgf %r2, 0(%r3)
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i64_sym_ext32(i64) -> b1 {
+  gv0 = symbol colocated %sym
+block0(v0: i64):
+  v1 = symbol_value.i64 gv0
+  v2 = sload32.i64 v1
+  v3 = icmp.i64 slt v0, v2
+  return v3
+}
+
+; check:  cgfrl %r2, %sym + 0
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i32(i32, i32) -> b1 {
+block0(v0: i32, v1: i32):
+  v2 = icmp.i32 slt v0, v1
+  return v2
+}
+
+; check:  cr %r2, %r3
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i32_imm16(i32) -> b1 {
+block0(v0: i32):
+  v1 = iconst.i32 1
+  v2 = icmp.i32 slt v0, v1
+  return v2
+}
+
+; check:  chi %r2, 1
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i32_imm(i32) -> b1 {
+block0(v0: i32):
+  v1 = iconst.i32 32768
+  v2 = icmp.i32 slt v0, v1
+  return v2
+}
+
+; check:  cfi %r2, 32768
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i32_mem(i32, i64) -> b1 {
+block0(v0: i32, v1: i64):
+  v2 = load.i32 v1
+  v3 = icmp.i32 slt v0, v2
+  return v3
+}
+
+; check:  c %r2, 0(%r3)
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i32_memoff(i32, i64) -> b1 {
+block0(v0: i32, v1: i64):
+  v2 = load.i32 v1+4096
+  v3 = icmp.i32 slt v0, v2
+  return v3
+}
+
+; check:  cy %r2, 4096(%r3)
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i32_sym(i32) -> b1 {
+  gv0 = symbol colocated %sym
+block0(v0: i32):
+  v1 = symbol_value.i64 gv0
+  v2 = load.i32 v1
+  v3 = icmp.i32 slt v0, v2
+  return v3
+}
+
+; check:  crl %r2, %sym + 0
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i32_mem_ext16(i32, i64) -> b1 {
+block0(v0: i32, v1: i64):
+  v2 = sload16.i32 v1
+  v3 = icmp.i32 slt v0, v2
+  return v3
+}
+
+; check:  ch %r2, 0(%r3)
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i32_memoff_ext16(i32, i64) -> b1 {
+block0(v0: i32, v1: i64):
+  v2 = sload16.i32 v1+4096
+  v3 = icmp.i32 slt v0, v2
+  return v3
+}
+
+; check:  chy %r2, 4096(%r3)
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i32_sym_ext16(i32) -> b1 {
+  gv0 = symbol colocated %sym
+block0(v0: i32):
+  v1 = symbol_value.i64 gv0
+  v2 = sload16.i32 v1
+  v3 = icmp.i32 slt v0, v2
+  return v3
+}
+
+; check:  chrl %r2, %sym + 0
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i16(i16, i16) -> b1 {
+block0(v0: i16, v1: i16):
+  v2 = icmp.i16 slt v0, v1
+  return v2
+}
+
+; check:  lhr %r2, %r2
+; nextln: lhr %r3, %r3
+; nextln: cr %r2, %r3
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i16_imm(i16) -> b1 {
+block0(v0: i16):
+  v1 = iconst.i16 1
+  v2 = icmp.i16 slt v0, v1
+  return v2
+}
+
+; check:  lhr %r2, %r2
+; nextln: chi %r2, 1
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i16_mem(i16, i64) -> b1 {
+block0(v0: i16, v1: i64):
+  v2 = load.i16 v1
+  v3 = icmp.i16 slt v0, v2
+  return v3
+}
+
+; check:  lhr %r2, %r2
+; nextln: ch %r2, 0(%r3)
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i16_sym(i16) -> b1 {
+  gv0 = symbol colocated %sym
+block0(v0: i16):
+  v1 = symbol_value.i64 gv0
+  v2 = load.i16 v1
+  v3 = icmp.i16 slt v0, v2
+  return v3
+}
+
+; check:  lhr %r2, %r2
+; nextln: chrl %r2, %sym + 0
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i8(i8, i8) -> b1 {
+block0(v0: i8, v1: i8):
+  v2 = icmp.i8 slt v0, v1
+  return v2
+}
+
+; check:  lbr %r2, %r2
+; nextln: lbr %r3, %r3
+; nextln: cr %r2, %r3
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i8_imm(i8) -> b1 {
+block0(v0: i8):
+  v1 = iconst.i8 1
+  v2 = icmp.i8 slt v0, v1
+  return v2
+}
+
+; check:  lbr %r2, %r2
+; nextln: chi %r2, 1
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_slt_i8_mem(i8, i64) -> b1 {
+block0(v0: i8, v1: i64):
+  v2 = load.i8 v1
+  v3 = icmp.i8 slt v0, v2
+  return v3
+}
+
+; check:  lbr %r2, %r2
+; nextln: lb %r3, 0(%r3)
+; nextln: cr %r2, %r3
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i64(i64, i64) -> b1 {
+block0(v0: i64, v1: i64):
+  v2 = icmp.i64 ult v0, v1
+  return v2
+}
+
+; check:  clgr %r2, %r3
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i64_ext32(i64, i32) -> b1 {
+block0(v0: i64, v1: i32):
+  v2 = uextend.i64 v1
+  v3 = icmp.i64 ult v0, v2
+  return v3
+}
+
+; check:  clgfr %r2, %r3
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i64_imm(i64) -> b1 {
+block0(v0: i64):
+  v1 = iconst.i64 1
+  v2 = icmp.i64 ult v0, v1
+  return v2
+}
+
+; check:  clgfi %r2, 1
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i64_mem(i64, i64) -> b1 {
+block0(v0: i64, v1: i64):
+  v2 = load.i64 v1
+  v3 = icmp.i64 ult v0, v2
+  return v3
+}
+
+; check:  clg %r2, 0(%r3)
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i64_sym(i64) -> b1 {
+  gv0 = symbol colocated %sym
+block0(v0: i64):
+  v1 = symbol_value.i64 gv0
+  v2 = load.i64 v1
+  v3 = icmp.i64 ult v0, v2
+  return v3
+}
+
+; check:  clgrl %r2, %sym + 0
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i64_mem_ext32(i64, i64) -> b1 {
+block0(v0: i64, v1: i64):
+  v2 = uload32.i64 v1
+  v3 = icmp.i64 ult v0, v2
+  return v3
+}
+
+; check:  clgf %r2, 0(%r3)
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i64_sym_ext32(i64) -> b1 {
+  gv0 = symbol colocated %sym
+block0(v0: i64):
+  v1 = symbol_value.i64 gv0
+  v2 = uload32.i64 v1
+  v3 = icmp.i64 ult v0, v2
+  return v3
+}
+
+; check:  clgfrl %r2, %sym + 0
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i64_sym_ext16(i64) -> b1 {
+  gv0 = symbol colocated %sym
+block0(v0: i64):
+  v1 = symbol_value.i64 gv0
+  v2 = uload16.i64 v1
+  v3 = icmp.i64 ult v0, v2
+  return v3
+}
+
+; check:  clghrl %r2, %sym + 0
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i32(i32, i32) -> b1 {
+block0(v0: i32, v1: i32):
+  v2 = icmp.i32 ult v0, v1
+  return v2
+}
+
+; check:  clr %r2, %r3
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i32_imm(i32) -> b1 {
+block0(v0: i32):
+  v1 = iconst.i32 1
+  v2 = icmp.i32 ult v0, v1
+  return v2
+}
+
+; check:  clfi %r2, 1
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i32_mem(i32, i64) -> b1 {
+block0(v0: i32, v1: i64):
+  v2 = load.i32 v1
+  v3 = icmp.i32 ult v0, v2
+  return v3
+}
+
+; check:  cl %r2, 0(%r3)
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i32_memoff(i32, i64) -> b1 {
+block0(v0: i32, v1: i64):
+  v2 = load.i32 v1+4096
+  v3 = icmp.i32 ult v0, v2
+  return v3
+}
+
+; check:  cly %r2, 4096(%r3)
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i32_sym(i32) -> b1 {
+  gv0 = symbol colocated %sym
+block0(v0: i32):
+  v1 = symbol_value.i64 gv0
+  v2 = load.i32 v1
+  v3 = icmp.i32 ult v0, v2
+  return v3
+}
+
+; check:  clrl %r2, %sym + 0
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i32_sym_ext16(i32) -> b1 {
+  gv0 = symbol colocated %sym
+block0(v0: i32):
+  v1 = symbol_value.i64 gv0
+  v2 = uload16.i32 v1
+  v3 = icmp.i32 ult v0, v2
+  return v3
+}
+
+; check:  clhrl %r2, %sym + 0
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i16(i16, i16) -> b1 {
+block0(v0: i16, v1: i16):
+  v2 = icmp.i16 ult v0, v1
+  return v2
+}
+
+; check:  llhr %r2, %r2
+; nextln: llhr %r3, %r3
+; nextln: clr %r2, %r3
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i16_imm(i16) -> b1 {
+block0(v0: i16):
+  v1 = iconst.i16 1
+  v2 = icmp.i16 ult v0, v1
+  return v2
+}
+
+; check:  llhr %r2, %r2
+; nextln: clfi %r2, 1
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i16_mem(i16, i64) -> b1 {
+block0(v0: i16, v1: i64):
+  v2 = load.i16 v1
+  v3 = icmp.i16 ult v0, v2
+  return v3
+}
+
+; check:  llhr %r2, %r2
+; nextln: llh %r3, 0(%r3)
+; nextln: clr %r2, %r3
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i16_mem(i16) -> b1 {
+  gv0 = symbol colocated %sym
+block0(v0: i16):
+  v1 = symbol_value.i64 gv0
+  v2 = load.i16 v1
+  v3 = icmp.i16 ult v0, v2
+  return v3
+}
+
+; check:  llhr %r2, %r2
+; nextln: clhrl %r2, %sym + 0
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i8(i8, i8) -> b1 {
+block0(v0: i8, v1: i8):
+  v2 = icmp.i8 ult v0, v1
+  return v2
+}
+
+; check:  llcr %r2, %r2
+; nextln: llcr %r3, %r3
+; nextln: clr %r2, %r3
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i8_imm(i8) -> b1 {
+block0(v0: i8):
+  v1 = iconst.i8 1
+  v2 = icmp.i8 ult v0, v1
+  return v2
+}
+
+; check:  llcr %r2, %r2
+; nextln: clfi %r2, 1
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
+function %icmp_ult_i8_mem(i8, i64) -> b1 {
+block0(v0: i8, v1: i64):
+  v2 = load.i8 v1
+  v3 = icmp.i8 ult v0, v2
+  return v3
+}
+
+; check:  llcr %r2, %r2
+; nextln: llc %r3, 0(%r3)
+; nextln: clr %r2, %r3
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+

cranelift/filetests/filetests/isa/s390x/jumptable.clif

@@ -0,0 +1,45 @@
+test compile
+target s390x
+
+function %f(i64) -> i64 {
+  jt0 = jump_table [block1, block2, block3]
+
+block0(v0: i64):
+  br_table v0, block4, jt0
+
+block1:
+  v1 = iconst.i64 1
+  jump block5(v1)
+
+block2:
+  v2 = iconst.i64 2
+  jump block5(v2)
+
+block3:
+  v3 = iconst.i64 3
+  jump block5(v3)
+
+block4:
+  v4 = iconst.i64 4
+  jump block5(v4)
+
+block5(v5: i64):
+  v6 = iadd.i64 v0, v5
+  return v6
+}
+
+; check:  clgfi %r2, 3 ; jghe label1 ; sllg %r4, %r2, 2 ; larl %r3, 18 ; lgf %r4, 0(%r4, %r3) ; agrk %r3, %r3, %r4 ; br %r3 ; jt_entries 
+
+; check:  lghi %r3, 1
+; nextln: jg
+
+; check:  lghi %r3, 2
+; nextln: jg
+
+; check:  lghi %r3, 3
+; nextln: jg
+
+; check:  agr %r2, %r3
+; nextln: br %r14
+
+

cranelift/filetests/filetests/isa/s390x/load-little.clif

@@ -0,0 +1,258 @@
+test compile
+target s390x
+
+function %load_i64(i64) -> i64 {
+block0(v0: i64):
+  v1 = load.i64 little v0
+  return v1
+}
+
+; check:  lrvg %r2, 0(%r2)
+; nextln: br %r14
+
+function %load_i64_sym() -> i64 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = load.i64 little v0
+  return v1
+}
+
+; check:  larl %r1, %sym + 0 ; lrvg %r2, 0(%r1)
+; nextln: br %r14
+
+function %uload8_i64(i64) -> i64 {
+block0(v0: i64):
+  v1 = uload8.i64 little v0
+  return v1
+}
+
+; check:  llgc %r2, 0(%r2)
+; nextln: br %r14
+
+function %sload8_i64(i64) -> i64 {
+block0(v0: i64):
+  v1 = sload8.i64 little v0
+  return v1
+}
+
+; check:  lgb %r2, 0(%r2)
+; nextln: br %r14
+
+function %uload16_i64(i64) -> i64 {
+block0(v0: i64):
+  v1 = uload16.i64 little v0
+  return v1
+}
+
+; check:  lrvh %r2, 0(%r2)
+; nextln: llghr %r2, %r2
+; nextln: br %r14
+
+function %uload16_i64_sym() -> i64 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = uload16.i64 little v0
+  return v1
+}
+
+; check:  larl %r1, %sym + 0 ; lrvh %r2, 0(%r1)
+; nextln: llghr %r2, %r2
+; nextln: br %r14
+
+function %sload16_i64(i64) -> i64 {
+block0(v0: i64):
+  v1 = sload16.i64 little v0
+  return v1
+}
+
+; check:  lrvh %r2, 0(%r2)
+; nextln: lghr %r2, %r2
+; nextln: br %r14
+
+function %sload16_i64_sym() -> i64 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = sload16.i64 little v0
+  return v1
+}
+
+; check:  larl %r1, %sym + 0 ; lrvh %r2, 0(%r1)
+; nextln: lghr %r2, %r2
+; nextln: br %r14
+
+function %uload32_i64(i64) -> i64 {
+block0(v0: i64):
+  v1 = uload32.i64 little v0
+  return v1
+}
+
+; check:  lrv %r2, 0(%r2)
+; nextln: llgfr %r2, %r2
+; nextln: br %r14
+
+function %uload32_i64_sym() -> i64 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = uload32.i64 little v0
+  return v1
+}
+
+; check:  larl %r1, %sym + 0 ; lrv %r2, 0(%r1)
+; nextln: llgfr %r2, %r2
+; nextln: br %r14
+
+function %sload32_i64(i64) -> i64 {
+block0(v0: i64):
+  v1 = sload32.i64 little v0
+  return v1
+}
+
+; check:  lrv %r2, 0(%r2)
+; nextln: lgfr %r2, %r2
+; nextln: br %r14
+
+function %sload32_i64_sym() -> i64 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = sload32.i64 little v0
+  return v1
+}
+
+; check:  larl %r1, %sym + 0 ; lrv %r2, 0(%r1)
+; nextln: lgfr %r2, %r2
+; nextln: br %r14
+
+function %load_i32(i64) -> i32 {
+block0(v0: i64):
+  v1 = load.i32 little v0
+  return v1
+}
+
+; check:  lrv %r2, 0(%r2)
+; nextln: br %r14
+
+function %load_i32_sym() -> i32 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = load.i32 little v0
+  return v1
+}
+
+; check:  larl %r1, %sym + 0 ; lrv %r2, 0(%r1)
+; nextln: br %r14
+
+function %uload8_i32(i64) -> i32 {
+block0(v0: i64):
+  v1 = uload8.i32 little v0
+  return v1
+}
+
+; check:  llc %r2, 0(%r2)
+; nextln: br %r14
+
+function %sload8_i32(i64) -> i32 {
+block0(v0: i64):
+  v1 = sload8.i32 little v0
+  return v1
+}
+
+; check:  lb %r2, 0(%r2)
+; nextln: br %r14
+
+function %uload16_i32(i64) -> i32 {
+block0(v0: i64):
+  v1 = uload16.i32 little v0
+  return v1
+}
+
+; check:  lrvh %r2, 0(%r2)
+; nextln: llhr %r2, %r2
+; nextln: br %r14
+
+function %uload16_i32_sym() -> i32 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = uload16.i32 little v0
+  return v1
+}
+
+; check:  larl %r1, %sym + 0 ; lrvh %r2, 0(%r1)
+; nextln: llhr %r2, %r2
+; nextln: br %r14
+
+function %sload16_i32(i64) -> i32 {
+block0(v0: i64):
+  v1 = sload16.i32 little v0
+  return v1
+}
+
+; check:  lrvh %r2, 0(%r2)
+; nextln: lhr %r2, %r2
+; nextln: br %r14
+
+function %sload16_i32_sym() -> i32 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = sload16.i32 little v0
+  return v1
+}
+
+; check:  larl %r1, %sym + 0 ; lrvh %r2, 0(%r1)
+; nextln: lhr %r2, %r2
+; nextln: br %r14
+
+function %load_i16(i64) -> i16 {
+block0(v0: i64):
+  v1 = load.i16 little v0
+  return v1
+}
+
+; check:  lrvh %r2, 0(%r2)
+; nextln: br %r14
+
+function %load_i16_sym() -> i16 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = load.i16 little v0
+  return v1
+}
+
+; check:  larl %r1, %sym + 0 ; lrvh %r2, 0(%r1)
+; nextln: br %r14
+
+function %uload8_i16(i64) -> i16 {
+block0(v0: i64):
+  v1 = uload8.i16 little v0
+  return v1
+}
+
+; check:  llc %r2, 0(%r2)
+; nextln: br %r14
+
+function %sload8_i16(i64) -> i16 {
+block0(v0: i64):
+  v1 = sload8.i16 little v0
+  return v1
+}
+
+; check:  lb %r2, 0(%r2)
+; nextln: br %r14
+
+function %load_i8(i64) -> i8 {
+block0(v0: i64):
+  v1 = load.i8 little v0
+  return v1
+}
+
+; check:  llc %r2, 0(%r2)
+; nextln: br %r14
+

cranelift/filetests/filetests/isa/s390x/load.clif

@@ -0,0 +1,264 @@
+test compile
+target s390x
+
+function %load_i64(i64) -> i64 {
+block0(v0: i64):
+  v1 = load.i64 v0
+  return v1
+}
+
+; check:  lg %r2, 0(%r2)
+; nextln: br %r14
+
+function %load_i64_sym() -> i64 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = load.i64 v0
+  return v1
+}
+
+; check:  lgrl %r2, %sym + 0
+; nextln: br %r14
+
+function %uload8_i64(i64) -> i64 {
+block0(v0: i64):
+  v1 = uload8.i64 v0
+  return v1
+}
+
+; check:  llgc %r2, 0(%r2)
+; nextln: br %r14
+
+function %sload8_i64(i64) -> i64 {
+block0(v0: i64):
+  v1 = sload8.i64 v0
+  return v1
+}
+
+; check:  lgb %r2, 0(%r2)
+; nextln: br %r14
+
+function %uload16_i64(i64) -> i64 {
+block0(v0: i64):
+  v1 = uload16.i64 v0
+  return v1
+}
+
+; check:  llgh %r2, 0(%r2)
+; nextln: br %r14
+
+function %uload16_i64_sym() -> i64 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = uload16.i64 v0
+  return v1
+}
+
+; check:  llghrl %r2, %sym + 0
+; nextln: br %r14
+
+function %sload16_i64(i64) -> i64 {
+block0(v0: i64):
+  v1 = sload16.i64 v0
+  return v1
+}
+
+; check:  lgh %r2, 0(%r2)
+; nextln: br %r14
+
+function %sload16_i64_sym() -> i64 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = sload16.i64 v0
+  return v1
+}
+
+; check:  lghrl %r2, %sym + 0
+; nextln: br %r14
+
+function %uload32_i64(i64) -> i64 {
+block0(v0: i64):
+  v1 = uload32.i64 v0
+  return v1
+}
+
+; check:  llgf %r2, 0(%r2)
+; nextln: br %r14
+
+function %uload32_i64_sym() -> i64 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = uload32.i64 v0
+  return v1
+}
+
+; check:  llgfrl %r2, %sym + 0
+; nextln: br %r14
+
+function %sload32_i64(i64) -> i64 {
+block0(v0: i64):
+  v1 = sload32.i64 v0
+  return v1
+}
+
+; check:  lgf %r2, 0(%r2)
+; nextln: br %r14
+
+function %sload32_i64_sym() -> i64 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = sload32.i64 v0
+  return v1
+}
+
+; check:  lgfrl %r2, %sym + 0
+; nextln: br %r14
+
+function %load_i32(i64) -> i32 {
+block0(v0: i64):
+  v1 = load.i32 v0
+  return v1
+}
+
+; check:  l %r2, 0(%r2)
+; nextln: br %r14
+
+function %load_i32_sym() -> i32 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = load.i32 v0
+  return v1
+}
+
+; check:  lrl %r2, %sym + 0
+; nextln: br %r14
+
+function %load_i32_off(i64) -> i32 {
+block0(v0: i64):
+  v1 = load.i32 v0+4096
+  return v1
+}
+
+; check:  ly %r2, 4096(%r2)
+; nextln: br %r14
+
+function %uload8_i32(i64) -> i32 {
+block0(v0: i64):
+  v1 = uload8.i32 v0
+  return v1
+}
+
+; check:  llc %r2, 0(%r2)
+; nextln: br %r14
+
+function %sload8_i32(i64) -> i32 {
+block0(v0: i64):
+  v1 = sload8.i32 v0
+  return v1
+}
+
+; check:  lb %r2, 0(%r2)
+; nextln: br %r14
+
+function %uload16_i32(i64) -> i32 {
+block0(v0: i64):
+  v1 = uload16.i32 v0
+  return v1
+}
+
+; check:  llh %r2, 0(%r2)
+; nextln: br %r14
+
+function %uload16_i32_sym() -> i32 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = uload16.i32 v0
+  return v1
+}
+
+; check:  llhrl %r2, %sym + 0
+; nextln: br %r14
+
+function %sload16_i32(i64) -> i32 {
+block0(v0: i64):
+  v1 = sload16.i32 v0
+  return v1
+}
+
+; check:  lh %r2, 0(%r2)
+; nextln: br %r14
+
+function %sload16_i32_off(i64) -> i32 {
+block0(v0: i64):
+  v1 = sload16.i32 v0+4096
+  return v1
+}
+
+; check:  lhy %r2, 4096(%r2)
+; nextln: br %r14
+
+function %sload16_i32_sym() -> i32 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = sload16.i32 v0
+  return v1
+}
+
+; check:  lhrl %r2, %sym + 0
+; nextln: br %r14
+
+function %load_i16(i64) -> i16 {
+block0(v0: i64):
+  v1 = load.i16 v0
+  return v1
+}
+
+; check:  llh %r2, 0(%r2)
+; nextln: br %r14
+
+function %load_i16_sym() -> i16 {
+  gv0 = symbol colocated %sym
+block0:
+  v0 = symbol_value.i64 gv0
+  v1 = load.i16 v0
+  return v1
+}
+
+; check:  llhrl %r2, %sym + 0
+; nextln: br %r14
+
+function %uload8_i16(i64) -> i16 {
+block0(v0: i64):
+  v1 = uload8.i16 v0
+  return v1
+}
+
+; check:  llc %r2, 0(%r2)
+; nextln: br %r14
+
+function %sload8_i16(i64) -> i16 {
+block0(v0: i64):
+  v1 = sload8.i16 v0
+  return v1
+}
+
+; check:  lb %r2, 0(%r2)
+; nextln: br %r14
+
+function %load_i8(i64) -> i8 {
+block0(v0: i64):
+  v1 = load.i8 v0
+  return v1
+}
+
+; check:  llc %r2, 0(%r2)
+; nextln: br %r14
+

cranelift/filetests/filetests/isa/s390x/multivalue-ret.clif

@@ -0,0 +1,79 @@
+test compile
+target s390x
+
+;; Test default (non-SpiderMonkey) ABI.
+function %f1() -> i64, i64, i64, i64 {
+block1:
+  v0 = iconst.i64 1
+  v1 = iconst.i64 2
+  v2 = iconst.i64 3
+  v3 = iconst.i64 4
+  return v0, v1, v2, v3
+}
+
+; check:  lghi %r2, 1
+; nextln: lghi %r3, 2
+; nextln: lghi %r4, 3
+; nextln: lghi %r5, 4
+; nextln: br %r14
+
+function %f1() -> i64, i64, i64, i64, i64, i64 {
+block1:
+  v0 = iconst.i64 1
+  v1 = iconst.i64 2
+  v2 = iconst.i64 3
+  v3 = iconst.i64 4
+  v4 = iconst.i64 5
+  v5 = iconst.i64 6
+  return v0, v1, v2, v3, v4, v5
+}
+
+; check:  stmg %r12, %r15, 96(%r15)
+; nextln: lgr %r14, %r2
+; nextln: lghi %r2, 1
+; nextln: lghi %r3, 2
+; nextln: lghi %r4, 3
+; nextln: lghi %r5, 4
+; nextln: lghi %r13, 5
+; nextln: lghi %r12, 6
+; nextln: stg %r13, 0(%r14)
+; nextln: stg %r12, 8(%r14)
+; nextln: lmg %r12, %r15, 96(%r15)
+; nextln: br %r14
+
+;; Test default (non-SpiderMonkey) ABI.
+function %f3() -> f64, f64, f64, f64 {
+block1:
+  v0 = f64const 0x0.0
+  v1 = f64const 0x1.0
+  v2 = f64const 0x2.0
+  v3 = f64const 0x3.0
+  return v0, v1, v2, v3
+}
+
+; check:  bras %r1, 12 ; data.f64 0 ; ld %f0, 0(%r1)
+; nextln: bras %r1, 12 ; data.f64 1 ; ld %f2, 0(%r1)
+; nextln: bras %r1, 12 ; data.f64 2 ; ld %f4, 0(%r1)
+; nextln: bras %r1, 12 ; data.f64 3 ; ld %f6, 0(%r1)
+; nextln: br %r14
+
+function %f4() -> f64, f64, f64, f64, f64, f64 {
+block1:
+  v0 = f64const 0x0.0
+  v1 = f64const 0x1.0
+  v2 = f64const 0x2.0
+  v3 = f64const 0x3.0
+  v4 = f64const 0x4.0
+  v5 = f64const 0x5.0
+  return v0, v1, v2, v3, v4, v5
+}
+
+; check:  bras %r1, 12 ; data.f64 0 ; ld %f0, 0(%r1)
+; nextln: bras %r1, 12 ; data.f64 1 ; ld %f2, 0(%r1)
+; nextln: bras %r1, 12 ; data.f64 2 ; ld %f4, 0(%r1)
+; nextln: bras %r1, 12 ; data.f64 3 ; ld %f6, 0(%r1)
+; nextln: bras %r1, 12 ; data.f64 4 ; ld %f1, 0(%r1)
+; nextln: bras %r1, 12 ; data.f64 5 ; ld %f3, 0(%r1)
+; nextln: std %f1, 0(%r2)
+; nextln: std %f3, 8(%r2)
+; nextln: br %r14

cranelift/filetests/filetests/isa/s390x/reftypes.clif

@@ -0,0 +1,101 @@
+test compile
+target s390x
+
+function %f0(r64, r64) -> r64 {
+block0(v0: r64, v1: r64):
+  return v1
+}
+
+; check:  lgr %r2, %r3
+; nextln: br %r14
+
+function %f1(r64) -> b1 {
+block0(v0: r64):
+  v1 = is_null v0
+  return v1
+}
+
+; check:  cghi %r2, 0
+; nextln: lhi %r2, 0
+; nextln: lochie %r2, 1
+; nextln: br %r14
+
+function %f2(r64) -> b1 {
+block0(v0: r64):
+  v1 = is_invalid v0
+  return v1
+}
+
+; check:  cghi %r2, -1
+; nextln: lhi %r2, 0
+; nextln: lochie %r2, 1
+; nextln: br %r14
+
+function %f3() -> r64 {
+block0:
+  v0 = null.r64
+  return v0
+}
+
+; check:  lghi %r2, 0
+; nextln: br %r14
+
+function %f4(r64, r64) -> r64, r64, r64 {
+    fn0 = %f(r64) -> b1
+    ss0 = explicit_slot 8
+
+block0(v0: r64, v1: r64):
+    v2 = call fn0(v0)
+    stack_store.r64 v0, ss0
+    brz v2, block1(v1, v0)
+    jump block2(v0, v1)
+
+block1(v3: r64, v4: r64):
+    jump block3(v3, v4)
+
+block2(v5: r64, v6: r64):
+    jump block3(v5, v6)
+
+block3(v7: r64, v8: r64):
+    v9 = stack_load.r64 ss0
+    return v7, v8, v9
+}
+
+; check: Block 0:
+; check:  stmg %r12, %r15, 96(%r15)
+; nextln: aghi %r15, -192
+; nextln: virtual_sp_offset_adjust 160
+; nextln: lgr %r13, %r2
+; nextln: lgr %r12, %r3
+; nextln: lgr %r2, %r13
+; nextln: bras %r1, 12 ; data %f + 0 ; lg %r3, 0(%r1)
+; nextln: stg %r2, 168(%r15)
+; nextln: stg %r13, 176(%r15)
+; nextln: stg %r12, 184(%r15)
+; nextln: (safepoint: slots [S0, S1, S2]
+; nextln: basr %r14, %r3
+; nextln: lg %r13, 176(%r15)
+; nextln: lg %r12, 184(%r15)
+; nextln: la %r3, 160(%r15)
+; nextln: stg %r13, 0(%r3)
+; nextln: llcr %r2, %r2
+; nextln: chi %r2, 0
+; nextln: jgnlh label1 ; jg label3
+; check: Block 1:
+; check:  jg label2
+; check: Block 2:
+; check:  lgr %r2, %r12
+; nextln: jg label5
+; check: Block 3:
+; check:  jg label4
+; check: Block 4:
+; check:  lgr %r2, %r13
+; nextln: lgr %r13, %r12
+; nextln: jg label5
+; check: Block 5:
+; check:  la %r3, 160(%r15)
+; nextln: lg %r3, 0(%r3)
+; nextln: lgr %r4, %r3
+; nextln: lgr %r3, %r13
+; nextln: lmg %r12, %r15, 288(%r15)
+; nextln: br %r14

cranelift/filetests/filetests/isa/s390x/saturating-ops.clif

@@ -0,0 +1,12 @@
+test compile
+target s390x
+
+; FIXME: not yet supported
+
+function %uaddsat64(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+;  v2 = uadd_sat.i64 v0, v1
+  v2 = iconst.i64 0
+  return v2
+}
+

cranelift/filetests/filetests/isa/s390x/shift-rotate.clif

@@ -0,0 +1,461 @@
+test compile
+target s390x
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; ROTR
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %rotr_i64_reg(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = rotr.i64 v0, v1
+  return v2
+}
+
+; check:  lcgr %r3, %r3
+; nextln: rllg %r2, %r2, 0(%r3)
+; nextln: br %r14
+
+function %rotr_i64_imm(i64) -> i64 {
+block0(v0: i64):
+  v1 = iconst.i32 17
+  v2 = rotr.i64 v0, v1
+  return v2
+}
+
+; check:  rllg %r2, %r2, 47
+; nextln: br %r14
+
+function %rotr_i32_reg(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = rotr.i32 v0, v1
+  return v2
+}
+
+; check:  lcr %r3, %r3
+; nextln: rll %r2, %r2, 0(%r3)
+; nextln: br %r14
+
+function %rotr_i32_imm(i32) -> i32 {
+block0(v0: i32):
+  v1 = iconst.i32 17
+  v2 = rotr.i32 v0, v1
+  return v2
+}
+
+; check:  rll %r2, %r2, 15
+; nextln: br %r14
+
+function %rotr_i16_reg(i16, i16) -> i16 {
+block0(v0: i16, v1: i16):
+  v2 = rotr.i16 v0, v1
+  return v2
+}
+
+; check:  llhr %r2, %r2
+; nextln: lr %r5, %r3
+; nextln: lcr %r4, %r3
+; nextln: nill %r5, 15
+; nextln: nill %r4, 15
+; nextln: sllk %r3, %r2, 0(%r5)
+; nextln: srlk %r2, %r2, 0(%r4)
+; nextln: ork %r2, %r3, %r2
+; nextln: br %r14
+
+function %rotr_i16_imm(i16) -> i16 {
+block0(v0: i16):
+  v1 = iconst.i32 10
+  v2 = rotr.i16 v0, v1
+  return v2
+}
+
+; check:  llhr %r2, %r2
+; nextln: sllk %r3, %r2, 6
+; nextln: srlk %r2, %r2, 10
+; nextln: ork %r2, %r3, %r2
+; nextln: br %r14
+
+function %rotr_i8_reg(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+  v2 = rotr.i8 v0, v1
+  return v2
+}
+
+; check:  llcr %r2, %r2
+; nextln: lr %r5, %r3
+; nextln: lcr %r4, %r3
+; nextln: nill %r5, 7
+; nextln: nill %r4, 7
+; nextln: sllk %r3, %r2, 0(%r5)
+; nextln: srlk %r2, %r2, 0(%r4)
+; nextln: ork %r2, %r3, %r2
+; nextln: br %r14
+
+function %rotr_i8_imm(i8) -> i8 {
+block0(v0: i8):
+  v1 = iconst.i32 3
+  v2 = rotr.i8 v0, v1
+  return v2
+}
+
+; check:  llcr %r2, %r2
+; nextln: sllk %r3, %r2, 5
+; nextln: srlk %r2, %r2, 3
+; nextln: ork %r2, %r3, %r2
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; ROTL
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %rotl_i64_reg(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = rotl.i64 v0, v1
+  return v2
+}
+
+; check:  rllg %r2, %r2, 0(%r3)
+; nextln: br %r14
+
+function %rotl_i64_imm(i64) -> i64 {
+block0(v0: i64):
+  v1 = iconst.i32 17
+  v2 = rotl.i64 v0, v1
+  return v2
+}
+
+; check:  rllg %r2, %r2, 17
+; nextln: br %r14
+
+function %rotl_i32_reg(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = rotl.i32 v0, v1
+  return v2
+}
+
+; check:  rll %r2, %r2, 0(%r3)
+; nextln: br %r14
+
+function %rotl_i32_imm(i32) -> i32 {
+block0(v0: i32):
+  v1 = iconst.i32 17
+  v2 = rotl.i32 v0, v1
+  return v2
+}
+
+; check:  rll %r2, %r2, 17
+; nextln: br %r14
+
+function %rotl_i16_reg(i16, i16) -> i16 {
+block0(v0: i16, v1: i16):
+  v2 = rotl.i16 v0, v1
+  return v2
+}
+
+; check:  llhr %r2, %r2
+; nextln: lr %r4, %r3
+; nextln: lcr %r3, %r3
+; nextln: nill %r4, 15
+; nextln: nill %r3, 15
+; nextln: sllk %r3, %r2, 0(%r3)
+; nextln: srlk %r2, %r2, 0(%r4)
+; nextln: ork %r2, %r3, %r2
+; nextln: br %r14
+
+function %rotl_i16_imm(i16) -> i16 {
+block0(v0: i16):
+  v1 = iconst.i32 10
+  v2 = rotl.i16 v0, v1
+  return v2
+}
+
+; check:  llhr %r2, %r2
+; nextln: sllk %r3, %r2, 10
+; nextln: srlk %r2, %r2, 6
+; nextln: ork %r2, %r3, %r2
+; nextln: br %r14
+
+function %rotl_i8_reg(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+  v2 = rotl.i8 v0, v1
+  return v2
+}
+
+; check:  llcr %r2, %r2
+; nextln: lr %r4, %r3
+; nextln: lcr %r3, %r3
+; nextln: nill %r4, 7
+; nextln: nill %r3, 7
+; nextln: sllk %r3, %r2, 0(%r3)
+; nextln: srlk %r2, %r2, 0(%r4)
+; nextln: ork %r2, %r3, %r2
+; nextln: br %r14
+
+function %rotr_i8_imm(i8) -> i8 {
+block0(v0: i8):
+  v1 = iconst.i32 3
+  v2 = rotl.i8 v0, v1
+  return v2
+}
+
+; check:  llcr %r2, %r2
+; nextln: sllk %r3, %r2, 3
+; nextln: srlk %r2, %r2, 5
+; nextln: ork %r2, %r3, %r2
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; USHR
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %ushr_i64_reg(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = ushr.i64 v0, v1
+  return v2
+}
+
+; check:  srlg %r2, %r2, 0(%r3)
+; nextln: br %r14
+
+function %ushr_i64_imm(i64) -> i64 {
+block0(v0: i64):
+  v1 = iconst.i32 17
+  v2 = ushr.i64 v0, v1
+  return v2
+}
+
+; check:  srlg %r2, %r2, 17
+; nextln: br %r14
+
+function %ushr_i32_reg(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = ushr.i32 v0, v1
+  return v2
+}
+
+; check:  srlk %r2, %r2, 0(%r3)
+; nextln: br %r14
+
+function %ushr_i32_imm(i32) -> i32 {
+block0(v0: i32):
+  v1 = iconst.i32 17
+  v2 = ushr.i32 v0, v1
+  return v2
+}
+
+; check:  srlk %r2, %r2, 17
+; nextln: br %r14
+
+function %ushr_i16_reg(i16, i16) -> i16 {
+block0(v0: i16, v1: i16):
+  v2 = ushr.i16 v0, v1
+  return v2
+}
+
+; FIXME: check shift count ?
+
+; check:  llhr %r2, %r2
+; nextln: nill %r3, 31
+; nextln: srlk %r2, %r2, 0(%r3)
+; nextln: br %r14
+
+function %ushr_i16_imm(i16) -> i16 {
+block0(v0: i16):
+  v1 = iconst.i32 10
+  v2 = ushr.i16 v0, v1
+  return v2
+}
+
+; check:  llhr %r2, %r2
+; nextln: srlk %r2, %r2, 10
+; nextln: br %r14
+
+function %ushr_i8_reg(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+  v2 = ushr.i8 v0, v1
+  return v2
+}
+
+; check:  llcr %r2, %r2
+; nextln: nill %r3, 31
+; nextln: srlk %r2, %r2, 0(%r3)
+; nextln: br %r14
+
+function %ushr_i8_imm(i8) -> i8 {
+block0(v0: i8):
+  v1 = iconst.i32 3
+  v2 = ushr.i8 v0, v1
+  return v2
+}
+
+; check:  llcr %r2, %r2
+; nextln: srlk %r2, %r2, 3
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; ISHL
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %ishl_i64_reg(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = ishl.i64 v0, v1
+  return v2
+}
+
+; check:  sllg %r2, %r2, 0(%r3)
+; nextln: br %r14
+
+function %ishl_i64_imm(i64) -> i64 {
+block0(v0: i64):
+  v1 = iconst.i32 17
+  v2 = ishl.i64 v0, v1
+  return v2
+}
+
+; check:  sllg %r2, %r2, 17
+; nextln: br %r14
+
+function %ishl_i32_reg(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = ishl.i32 v0, v1
+  return v2
+}
+
+; check:  sllk %r2, %r2, 0(%r3)
+; nextln: br %r14
+
+function %ishl_i32_imm(i32) -> i32 {
+block0(v0: i32):
+  v1 = iconst.i32 17
+  v2 = ishl.i32 v0, v1
+  return v2
+}
+
+; check:  sllk %r2, %r2, 17
+; nextln: br %r14
+
+function %ishl_i16_reg(i16, i16) -> i16 {
+block0(v0: i16, v1: i16):
+  v2 = ishl.i16 v0, v1
+  return v2
+}
+
+; check:  nill %r3, 31
+; nextln: sllk %r2, %r2, 0(%r3)
+; nextln: br %r14
+
+function %ishl_i16_imm(i16) -> i16 {
+block0(v0: i16):
+  v1 = iconst.i32 10
+  v2 = ishl.i16 v0, v1
+  return v2
+}
+
+; check:  sllk %r2, %r2, 10
+; nextln: br %r14
+
+function %ishl_i8_reg(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+  v2 = ishl.i8 v0, v1
+  return v2
+}
+
+; check:  nill %r3, 31
+; nextln: sllk %r2, %r2, 0(%r3)
+; nextln: br %r14
+
+function %ishl_i8_imm(i8) -> i8 {
+block0(v0: i8):
+  v1 = iconst.i32 3
+  v2 = ishl.i8 v0, v1
+  return v2
+}
+
+; check:  sllk %r2, %r2, 3
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; SSHR
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %sshr_i64_reg(i64, i64) -> i64 {
+block0(v0: i64, v1: i64):
+  v2 = sshr.i64 v0, v1
+  return v2
+}
+
+; check:  srag %r2, %r2, 0(%r3)
+; nextln: br %r14
+
+function %sshr_i64_imm(i64) -> i64 {
+block0(v0: i64):
+  v1 = iconst.i32 17
+  v2 = sshr.i64 v0, v1
+  return v2
+}
+
+; check:  srag %r2, %r2, 17
+; nextln: br %r14
+
+function %sshr_i32_reg(i32, i32) -> i32 {
+block0(v0: i32, v1: i32):
+  v2 = sshr.i32 v0, v1
+  return v2
+}
+
+; check:  srak %r2, %r2, 0(%r3)
+; nextln: br %r14
+
+function %sshr_i32_imm(i32) -> i32 {
+block0(v0: i32):
+  v1 = iconst.i32 17
+  v2 = sshr.i32 v0, v1
+  return v2
+}
+
+; check:  srak %r2, %r2, 17
+; nextln: br %r14
+
+function %sshr_i16_reg(i16, i16) -> i16 {
+block0(v0: i16, v1: i16):
+  v2 = sshr.i16 v0, v1
+  return v2
+}
+
+; check:  lhr %r2, %r2
+; nextln: nill %r3, 31
+; nextln: srak %r2, %r2, 0(%r3)
+; nextln: br %r14
+
+function %sshr_i16_imm(i16) -> i16 {
+block0(v0: i16):
+  v1 = iconst.i32 10
+  v2 = sshr.i16 v0, v1
+  return v2
+}
+
+; check:  lhr %r2, %r2
+; nextln: srak %r2, %r2, 10
+; nextln: br %r14
+
+function %sshr_i8_reg(i8, i8) -> i8 {
+block0(v0: i8, v1: i8):
+  v2 = sshr.i8 v0, v1
+  return v2
+}
+
+; check:  lbr %r2, %r2
+; nextln: nill %r3, 31
+; nextln: srak %r2, %r2, 0(%r3)
+; nextln: br %r14
+
+function %sshr_i8_imm(i8) -> i8 {
+block0(v0: i8):
+  v1 = iconst.i32 3
+  v2 = sshr.i8 v0, v1
+  return v2
+}
+
+; check:  lbr %r2, %r2
+; nextln: srak %r2, %r2, 3
+; nextln: br %r14
+

cranelift/filetests/filetests/isa/s390x/stack-limit.clif

@@ -0,0 +1,175 @@
+test compile
+target s390x
+
+function %foo() {
+block0:
+    return
+}
+
+function %stack_limit_leaf_zero(i64 stack_limit) {
+block0(v0: i64):
+    return
+}
+
+; check:  br %r14
+
+function %stack_limit_gv_leaf_zero(i64 vmctx) {
+    gv0 = vmctx
+    gv1 = load.i64 notrap aligned gv0
+    gv2 = load.i64 notrap aligned gv1+4
+    stack_limit = gv2
+block0(v0: i64):
+    return
+}
+
+; check:  br %r14
+
+
+function %stack_limit_call_zero(i64 stack_limit) {
+    fn0 = %foo()
+block0(v0: i64):
+    call fn0()
+    return
+}
+
+; check:  clgrtle %r15, %r2
+; nextln: stmg %r14, %r15, 112(%r15)
+; nextln: aghi %r15, -160
+; nextln: virtual_sp_offset_adjust 160
+; nextln: bras %r1, 12 ; data %foo + 0 ; lg %r2, 0(%r1)
+; nextln: basr %r14, %r2
+; nextln: lmg %r14, %r15, 272(%r15)
+; nextln: br %r14
+
+function %stack_limit_gv_call_zero(i64 vmctx) {
+    gv0 = vmctx
+    gv1 = load.i64 notrap aligned gv0
+    gv2 = load.i64 notrap aligned gv1+4
+    stack_limit = gv2
+    fn0 = %foo()
+block0(v0: i64):
+    call fn0()
+    return
+}
+
+; check:  lg %r1, 0(%r2)
+; nextln: lg %r1, 4(%r1)
+; nextln: clgrtle %r15, %r1
+; nextln: stmg %r14, %r15, 112(%r15)
+; nextln: aghi %r15, -160
+; nextln: virtual_sp_offset_adjust 160
+; nextln: bras %r1, 12 ; data %foo + 0 ; lg %r2, 0(%r1)
+; nextln: basr %r14, %r2
+; nextln: lmg %r14, %r15, 272(%r15)
+; nextln: br %r14
+
+function %stack_limit(i64 stack_limit) {
+    ss0 = explicit_slot 168
+block0(v0: i64):
+    return
+}
+
+; check: la %r1, 168(%r2)
+; nextln: clgrtle %r15, %r1
+; nextln: aghi %r15, -168
+; nextln: aghi %r15, 168
+; nextln: br %r14
+
+function %large_stack_limit(i64 stack_limit) {
+    ss0 = explicit_slot 400000
+block0(v0: i64):
+    return
+}
+
+; check:  clgrtle %r15, %r2
+; nextln: lay %r1, 400000(%r2)
+; nextln: clgrtle %r15, %r1
+; nextln: agfi %r15, -400000
+; nextln: agfi %r15, 400000
+; nextln: br %r14
+
+function %huge_stack_limit(i64 stack_limit) {
+    ss0 = explicit_slot 4000000
+block0(v0: i64):
+    return
+}
+
+; check:  clgrtle %r15, %r2
+; nextln: lgr %r1, %r2
+; nextln: algfi %r1, 4000000
+; nextln: clgrtle %r15, %r1
+; nextln: agfi %r15, -4000000
+; nextln: agfi %r15, 4000000
+; nextln: br %r14
+
+function %limit_preamble(i64 vmctx) {
+    gv0 = vmctx
+    gv1 = load.i64 notrap aligned gv0
+    gv2 = load.i64 notrap aligned gv1+4
+    stack_limit = gv2
+    ss0 = explicit_slot 20
+block0(v0: i64):
+    return
+}
+
+; check:  lg %r1, 0(%r2)
+; nextln: lg %r1, 4(%r1)
+; nextln: la %r1, 24(%r1)
+; nextln: clgrtle %r15, %r1
+; nextln: aghi %r15, -24
+; nextln: aghi %r15, 24
+; nextln: br %r14
+
+function %limit_preamble_large(i64 vmctx) {
+    gv0 = vmctx
+    gv1 = load.i64 notrap aligned gv0
+    gv2 = load.i64 notrap aligned gv1+4
+    stack_limit = gv2
+    ss0 = explicit_slot 400000
+block0(v0: i64):
+    return
+}
+
+; check:  lg %r1, 0(%r2)
+; nextln: lg %r1, 4(%r1)
+; nextln: clgrtle %r15, %r1
+; nextln: lay %r1, 400000(%r1)
+; nextln: clgrtle %r15, %r1
+; nextln: agfi %r15, -400000
+; nextln: agfi %r15, 400000
+; nextln: br %r14
+
+function %limit_preamble_huge(i64 vmctx) {
+    gv0 = vmctx
+    gv1 = load.i64 notrap aligned gv0
+    gv2 = load.i64 notrap aligned gv1+4
+    stack_limit = gv2
+    ss0 = explicit_slot 4000000
+block0(v0: i64):
+    return
+}
+
+; check:  lg %r1, 0(%r2)
+; nextln: lg %r1, 4(%r1)
+; nextln: clgrtle %r15, %r1
+; nextln: algfi %r1, 4000000
+; nextln: clgrtle %r15, %r1
+; nextln: agfi %r15, -4000000
+; nextln: agfi %r15, 4000000
+; nextln: br %r14
+
+function %limit_preamble_huge_offset(i64 vmctx) {
+    gv0 = vmctx
+    gv1 = load.i64 notrap aligned gv0+1000000
+    stack_limit = gv1
+    ss0 = explicit_slot 20
+block0(v0: i64):
+    return
+}
+
+; check:  lgfi %r1, 1000000 ; lg %r1, 0(%r1,%r2)
+; nextln: la %r1, 24(%r1)
+; nextln: clgrtle %r15, %r1
+; nextln: aghi %r15, -24
+; nextln: aghi %r15, 24
+; nextln: br %r14

cranelift/filetests/filetests/isa/s390x/stack.clif

@@ -0,0 +1,93 @@
+test compile
+target s390x
+
+; FIXME: Should allocate register save area.
+
+function %stack_addr_small() -> i64 {
+ss0 = explicit_slot 8
+
+block0:
+  v0 = stack_addr.i64 ss0
+  return v0
+}
+
+; check:  aghi %r15, -8
+; nextln: la %r2, 0(%r15)
+; nextln: aghi %r15, 8
+; nextln: br %r14
+
+function %stack_addr_big() -> i64 {
+ss0 = explicit_slot 100000
+ss1 = explicit_slot 8
+
+block0:
+  v0 = stack_addr.i64 ss0
+  return v0
+}
+
+; check:  agfi %r15, -100008
+; nextln: la %r2, 0(%r15)
+; nextln: agfi %r15, 100008
+; nextln: br %r14
+
+; FIXME: don't use stack_addr legalization for stack_load and stack_store
+
+function %stack_load_small() -> i64 {
+ss0 = explicit_slot 8
+
+block0:
+  v0 = stack_load.i64 ss0
+  return v0
+}
+
+; check:  aghi %r15, -8
+; nextln: la %r2, 0(%r15)
+; nextln: lg %r2, 0(%r2)
+; nextln: aghi %r15, 8
+; nextln: br %r14
+
+function %stack_load_big() -> i64 {
+ss0 = explicit_slot 100000
+ss1 = explicit_slot 8
+
+block0:
+  v0 = stack_load.i64 ss0
+  return v0
+}
+
+; check:  agfi %r15, -100008
+; nextln: la %r2, 0(%r15)
+; nextln: lg %r2, 0(%r2)
+; nextln: agfi %r15, 100008
+; nextln: br %r14
+
+
+function %stack_store_small(i64) {
+ss0 = explicit_slot 8
+
+block0(v0: i64):
+  stack_store.i64 v0, ss0
+  return
+}
+
+; check:  aghi %r15, -8
+; nextln: la %r3, 0(%r15)
+; nextln: stg %r2, 0(%r3)
+; nextln: aghi %r15, 8
+; nextln: br %r14
+
+function %stack_store_big(i64) {
+ss0 = explicit_slot 100000
+ss1 = explicit_slot 8
+
+block0(v0: i64):
+  stack_store.i64 v0, ss0
+  return
+}
+
+; check:  agfi %r15, -100008
+; nextln: la %r3, 0(%r15)
+; nextln: stg %r2, 0(%r3)
+; nextln: agfi %r15, 100008
+; nextln: br %r14
+

cranelift/filetests/filetests/isa/s390x/store-little.clif

@@ -0,0 +1,281 @@
+test compile
+target s390x
+
+function %store_i64(i64, i64) {
+block0(v0: i64, v1: i64):
+  store.i64 little v0, v1
+  return
+}
+
+; check:  strvg %r2, 0(%r3)
+; nextln: br %r14
+
+function %store_i64_sym(i64) {
+  gv0 = symbol colocated %sym
+block0(v0: i64):
+  v1 = symbol_value.i64 gv0
+  store.i64 little v0, v1
+  return
+}
+
+; check:  larl %r1, %sym + 0 ; strvg %r2, 0(%r1)
+; nextln: br %r14
+
+function %store_imm_i64(i64) {
+block0(v0: i64):
+  v1 = iconst.i64 12345
+  store.i64 little v1, v0
+  return
+}
+
+; check:  lghi %r3, 12345
+; nextln: strvg %r3, 0(%r2)
+; nextln: br %r14
+
+function %istore8_i64(i64, i64) {
+block0(v0: i64, v1: i64):
+  istore8.i64 little v0, v1
+  return
+}
+
+; check:  stc %r2, 0(%r3)
+; nextln: br %r14
+
+function %istore8_imm_i64(i64) {
+block0(v0: i64):
+  v1 = iconst.i64 123
+  istore8.i64 little v1, v0
+  return
+}
+
+; check:  mvi 0(%r2), 123
+; nextln: br %r14
+
+function %istore16_i64(i64, i64) {
+block0(v0: i64, v1: i64):
+  istore16.i64 little v0, v1
+  return
+}
+
+; check:  strvh %r2, 0(%r3)
+; nextln: br %r14
+
+function %istore16_i64_sym(i64) {
+  gv0 = symbol colocated %sym
+block0(v0: i64):
+  v1 = symbol_value.i64 gv0
+  istore16.i64 little v0, v1
+  return
+}
+
+; check:  larl %r1, %sym + 0 ; strvh %r2, 0(%r1)
+; nextln: br %r14
+
+function %istore16_imm_i64(i64) {
+block0(v0: i64):
+  v1 = iconst.i64 12345
+  istore16.i64 little v1, v0
+  return
+}
+
+; check:  mvhhi 0(%r2), 14640
+; nextln: br %r14
+
+function %istore32_i64(i64, i64) {
+block0(v0: i64, v1: i64):
+  istore32.i64 little v0, v1
+  return
+}
+
+; check:  strv %r2, 0(%r3)
+; nextln: br %r14
+
+function %istore32_i64_sym(i64) {
+  gv0 = symbol colocated %sym
+block0(v0: i64):
+  v1 = symbol_value.i64 gv0
+  istore32.i64 little v0, v1
+  return
+}
+
+; check:  larl %r1, %sym + 0 ; strv %r2, 0(%r1)
+; nextln: br %r14
+
+function %istore32_imm_i64(i64) {
+block0(v0: i64):
+  v1 = iconst.i64 12345
+  istore32.i64 little v1, v0
+  return
+}
+
+; check:  lghi %r3, 12345
+; nextln: strv %r3, 0(%r2)
+; nextln: br %r14
+
+function %store_i32(i32, i64) {
+block0(v0: i32, v1: i64):
+  store.i32 little v0, v1
+  return
+}
+
+; check:  strv %r2, 0(%r3)
+; nextln: br %r14
+
+function %store_i32_sym(i32) {
+  gv0 = symbol colocated %sym
+block0(v0: i32):
+  v1 = symbol_value.i64 gv0
+  store.i32 little v0, v1
+  return
+}
+
+; check:  larl %r1, %sym + 0 ; strv %r2, 0(%r1)
+; nextln: br %r14
+
+function %store_imm_i32(i64) {
+block0(v0: i64):
+  v1 = iconst.i32 12345
+  store.i32 little v1, v0
+  return
+}
+
+; check:  lhi %r3, 12345
+; nextln: strv %r3, 0(%r2)
+; nextln: br %r14
+
+function %istore8_i32(i32, i64) {
+block0(v0: i32, v1: i64):
+  istore8.i32 little v0, v1
+  return
+}
+
+; check:  stc %r2, 0(%r3)
+; nextln: br %r14
+
+function %istore8_imm_i32(i64) {
+block0(v0: i64):
+  v1 = iconst.i32 123
+  istore8.i32 little v1, v0
+  return
+}
+
+; check:  mvi 0(%r2), 123
+; nextln: br %r14
+
+function %istore16_i32(i32, i64) {
+block0(v0: i32, v1: i64):
+  istore16.i32 little v0, v1
+  return
+}
+
+; check:  strvh %r2, 0(%r3)
+; nextln: br %r14
+
+function %istore16_i32_sym(i32) {
+  gv0 = symbol colocated %sym
+block0(v0: i32):
+  v1 = symbol_value.i64 gv0
+  istore16.i32 little v0, v1
+  return
+}
+
+; check:  larl %r1, %sym + 0 ; strvh %r2, 0(%r1)
+; nextln: br %r14
+
+function %istore16_imm_i32(i64) {
+block0(v0: i64):
+  v1 = iconst.i32 12345
+  istore16.i32 little v1, v0
+  return
+}
+
+; check:  mvhhi 0(%r2), 14640
+; nextln: br %r14
+
+function %store_i16(i16, i64) {
+block0(v0: i16, v1: i64):
+  store.i16 little v0, v1
+  return
+}
+
+; check:  strvh %r2, 0(%r3)
+; nextln: br %r14
+
+function %store_i16_sym(i16) {
+  gv0 = symbol colocated %sym
+block0(v0: i16):
+  v1 = symbol_value.i64 gv0
+  store.i16 little v0, v1
+  return
+}
+
+; check:  larl %r1, %sym + 0 ; strvh %r2, 0(%r1)
+; nextln: br %r14
+
+function %store_imm_i16(i64) {
+block0(v0: i64):
+  v1 = iconst.i16 12345
+  store.i16 little v1, v0
+  return
+}
+
+; check:  mvhhi 0(%r2), 14640
+; nextln: br %r14
+
+function %istore8_i16(i16, i64) {
+block0(v0: i16, v1: i64):
+  istore8.i16 little v0, v1
+  return
+}
+
+; check:  stc %r2, 0(%r3)
+; nextln: br %r14
+
+function %istore8_imm_i16(i64) {
+block0(v0: i64):
+  v1 = iconst.i16 123
+  istore8.i16 little v1, v0
+  return
+}
+
+; check:  mvi 0(%r2), 123
+; nextln: br %r14
+
+function %store_i8(i8, i64) {
+block0(v0: i8, v1: i64):
+  store.i8 little v0, v1
+  return
+}
+
+; check:  stc %r2, 0(%r3)
+; nextln: br %r14
+
+function %store_i8_off(i8, i64) {
+block0(v0: i8, v1: i64):
+  store.i8 little v0, v1+4096
+  return
+}
+
+; check:  stcy %r2, 4096(%r3)
+; nextln: br %r14
+
+function %store_imm_i8(i64) {
+block0(v0: i64):
+  v1 = iconst.i8 123
+  store.i8 little v1, v0
+  return
+}
+
+; check:  mvi 0(%r2), 123
+; nextln: br %r14
+
+function %store_imm_i8_off(i64) {
+block0(v0: i64):
+  v1 = iconst.i8 123
+  store.i8 little v1, v0+4096
+  return
+}
+
+; check:  mviy 4096(%r2), 123
+; nextln: br %r14
+

cranelift/filetests/filetests/isa/s390x/store.clif

@@ -0,0 +1,296 @@
+test compile
+target s390x
+
+function %store_i64(i64, i64) {
+block0(v0: i64, v1: i64):
+  store.i64 v0, v1
+  return
+}
+
+; check:  stg %r2, 0(%r3)
+; nextln: br %r14
+
+function %store_i64_sym(i64) {
+  gv0 = symbol colocated %sym
+block0(v0: i64):
+  v1 = symbol_value.i64 gv0
+  store.i64 v0, v1
+  return
+}
+
+; check:  stgrl %r2, %sym + 0
+; nextln: br %r14
+
+function %store_imm_i64(i64) {
+block0(v0: i64):
+  v1 = iconst.i64 12345
+  store.i64 v1, v0
+  return
+}
+
+; check:  mvghi 0(%r2), 12345
+; nextln: br %r14
+
+function %istore8_i64(i64, i64) {
+block0(v0: i64, v1: i64):
+  istore8.i64 v0, v1
+  return
+}
+
+; check:  stc %r2, 0(%r3)
+; nextln: br %r14
+
+function %istore8_imm_i64(i64) {
+block0(v0: i64):
+  v1 = iconst.i64 123
+  istore8.i64 v1, v0
+  return
+}
+
+; check:  mvi 0(%r2), 123
+; nextln: br %r14
+
+function %istore16_i64(i64, i64) {
+block0(v0: i64, v1: i64):
+  istore16.i64 v0, v1
+  return
+}
+
+; check:  sth %r2, 0(%r3)
+; nextln: br %r14
+
+function %istore16_i64_sym(i64) {
+  gv0 = symbol colocated %sym
+block0(v0: i64):
+  v1 = symbol_value.i64 gv0
+  istore16.i64 v0, v1
+  return
+}
+
+; check:  sthrl %r2, %sym + 0
+; nextln: br %r14
+
+function %istore16_imm_i64(i64) {
+block0(v0: i64):
+  v1 = iconst.i64 12345
+  istore16.i64 v1, v0
+  return
+}
+
+; check:  mvhhi 0(%r2), 12345
+; nextln: br %r14
+
+function %istore32_i64(i64, i64) {
+block0(v0: i64, v1: i64):
+  istore32.i64 v0, v1
+  return
+}
+
+; check:  st %r2, 0(%r3)
+; nextln: br %r14
+
+function %istore32_i64_sym(i64) {
+  gv0 = symbol colocated %sym
+block0(v0: i64):
+  v1 = symbol_value.i64 gv0
+  istore32.i64 v0, v1
+  return
+}
+
+; check:  strl %r2, %sym + 0
+; nextln: br %r14
+
+function %istore32_imm_i64(i64) {
+block0(v0: i64):
+  v1 = iconst.i64 12345
+  istore32.i64 v1, v0
+  return
+}
+
+; check:  mvhi 0(%r2), 12345
+; nextln: br %r14
+
+function %store_i32(i32, i64) {
+block0(v0: i32, v1: i64):
+  store.i32 v0, v1
+  return
+}
+
+; check:  st %r2, 0(%r3)
+; nextln: br %r14
+
+function %store_i32_sym(i32) {
+  gv0 = symbol colocated %sym
+block0(v0: i32):
+  v1 = symbol_value.i64 gv0
+  store.i32 v0, v1
+  return
+}
+
+; check:  strl %r2, %sym + 0
+; nextln: br %r14
+
+function %store_i32_off(i32, i64) {
+block0(v0: i32, v1: i64):
+  store.i32 v0, v1+4096
+  return
+}
+
+; check:  sty %r2, 4096(%r3)
+; nextln: br %r14
+
+function %store_imm_i32(i64) {
+block0(v0: i64):
+  v1 = iconst.i32 12345
+  store.i32 v1, v0
+  return
+}
+
+; check:  mvhi 0(%r2), 12345
+; nextln: br %r14
+
+function %istore8_i32(i32, i64) {
+block0(v0: i32, v1: i64):
+  istore8.i32 v0, v1
+  return
+}
+
+; check:  stc %r2, 0(%r3)
+; nextln: br %r14
+
+function %istore8_imm_i32(i64) {
+block0(v0: i64):
+  v1 = iconst.i32 123
+  istore8.i32 v1, v0
+  return
+}
+
+; check:  mvi 0(%r2), 123
+; nextln: br %r14
+
+function %istore16_i32(i32, i64) {
+block0(v0: i32, v1: i64):
+  istore16.i32 v0, v1
+  return
+}
+
+; check:  sth %r2, 0(%r3)
+; nextln: br %r14
+
+function %istore16_i32_sym(i32) {
+  gv0 = symbol colocated %sym
+block0(v0: i32):
+  v1 = symbol_value.i64 gv0
+  istore16.i32 v0, v1
+  return
+}
+
+; check:  sthrl %r2, %sym + 0
+; nextln: br %r14
+
+function %istore16_imm_i32(i64) {
+block0(v0: i64):
+  v1 = iconst.i32 12345
+  istore16.i32 v1, v0
+  return
+}
+
+; check:  mvhhi 0(%r2), 12345
+; nextln: br %r14
+
+function %store_i16(i16, i64) {
+block0(v0: i16, v1: i64):
+  store.i16 v0, v1
+  return
+}
+
+; check:  sth %r2, 0(%r3)
+; nextln: br %r14
+
+function %store_i16_sym(i16) {
+  gv0 = symbol colocated %sym
+block0(v0: i16):
+  v1 = symbol_value.i64 gv0
+  store.i16 v0, v1
+  return
+}
+
+; check:  sthrl %r2, %sym + 0
+; nextln: br %r14
+
+function %store_i16_off(i16, i64) {
+block0(v0: i16, v1: i64):
+  store.i16 v0, v1+4096
+  return
+}
+
+; check:  sthy %r2, 4096(%r3)
+; nextln: br %r14
+
+function %store_imm_i16(i64) {
+block0(v0: i64):
+  v1 = iconst.i16 12345
+  store.i16 v1, v0
+  return
+}
+
+; check:  mvhhi 0(%r2), 12345
+; nextln: br %r14
+
+function %istore8_i16(i16, i64) {
+block0(v0: i16, v1: i64):
+  istore8.i16 v0, v1
+  return
+}
+
+; check:  stc %r2, 0(%r3)
+; nextln: br %r14
+
+function %istore8_imm_i16(i64) {
+block0(v0: i64):
+  v1 = iconst.i16 123
+  istore8.i16 v1, v0
+  return
+}
+
+; check:  mvi 0(%r2), 123
+; nextln: br %r14
+
+function %store_i8(i8, i64) {
+block0(v0: i8, v1: i64):
+  store.i8 v0, v1
+  return
+}
+
+; check:  stc %r2, 0(%r3)
+; nextln: br %r14
+
+function %store_i8_off(i8, i64) {
+block0(v0: i8, v1: i64):
+  store.i8 v0, v1+4096
+  return
+}
+
+; check:  stcy %r2, 4096(%r3)
+; nextln: br %r14
+
+function %store_imm_i8(i64) {
+block0(v0: i64):
+  v1 = iconst.i8 123
+  store.i8 v1, v0
+  return
+}
+
+; check:  mvi 0(%r2), 123
+; nextln: br %r14
+
+function %store_imm_i8_off(i64) {
+block0(v0: i64):
+  v1 = iconst.i8 123
+  store.i8 v1, v0+4096
+  return
+}
+
+; check:  mviy 4096(%r2), 123
+; nextln: br %r14
+

cranelift/filetests/filetests/isa/s390x/symbols.clif

@@ -0,0 +1,54 @@
+test compile
+target s390x
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; SYMBOL_VALUE
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %symbol_value() -> i64 {
+  gv0 = symbol %my_global
+
+block0:
+  v0 = symbol_value.i64 gv0
+  return v0
+}
+
+; check:  bras %r1, 12 ; data %my_global + 0 ; lg %r2, 0(%r1)
+; nextln: br %r14
+
+function %symbol_value_colocated() -> i64 {
+  gv0 = symbol colocated %my_global_colo
+
+block0:
+  v0 = symbol_value.i64 gv0
+  return v0
+}
+
+; check:  larl %r2, %my_global_colo + 0
+; nextln: br %r14
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; FUNC_ADDR
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %func_addr() -> i64 {
+    fn0 = %my_func(i64) -> i64
+
+block0:
+    v0 = func_addr.i64 fn0
+    return v0
+}
+
+; check:  bras %r1, 12 ; data %my_func + 0 ; lg %r2, 0(%r1)
+; nextln: br %r14
+
+function %func_addr_colocated() -> i64 {
+    fn0 = colocated %my_func_colo(i64) -> i64
+
+block0:
+    v0 = func_addr.i64 fn0
+    return v0
+}
+
+; check:  larl %r2, %my_func_colo + 0
+; nextln: br %r14

cranelift/filetests/filetests/isa/s390x/traps.clif

@@ -0,0 +1,91 @@
+test compile
+target s390x
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; TRAP/RESUMABLE_TRAP
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %trap() {
+block0:
+  trap user0
+}
+
+; check: trap
+
+function %resumable_trap() {
+block0:
+  trap user0
+}
+
+; check: trap
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; TRAPZ
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %trapz(i64) {
+block0(v0: i64):
+  v1 = iconst.i64 42
+  v2 = icmp eq v0, v1
+  trapz v2, user0
+  return
+}
+
+; FIXME: Does not use TrapIf internally as trapz is expanded.
+; check: Block 0
+; check:  clgfi %r2, 42
+; nextln: jge label1 ; jg label2
+; check: Block 1:
+; check:  br %r14
+; check: Block 2:
+; check:  trap
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; TRAPNZ/RESUMABLE_TRAPNZ
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %trapnz(i64) {
+block0(v0: i64):
+  v1 = iconst.i64 42
+  v2 = icmp eq v0, v1
+  trapnz v2, user0
+  return
+}
+
+; FIXME: Does not use TrapIf internally as trapnz is expanded.
+; check: Block 0
+; check:  clgfi %r2, 42
+; nextln: jgne label1 ; jg label2
+; check: Block 1:
+; check:  br %r14
+; check: Block 2:
+; check:  trap
+
+function %resumable_trapnz(i64) {
+block0(v0: i64):
+  v1 = iconst.i64 42
+  v2 = icmp eq v0, v1
+  trapnz v2, user0
+  return
+}
+
+; FIXME: Does not use TrapIf internally as resumable_trapnz is expanded.
+; check: Block 0
+; check:  clgfi %r2, 42
+; nextln: jgne label1 ; jg label2
+; check: Block 1:
+; check:  br %r14
+; check: Block 2:
+; check:  trap
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; DEBUGTRAP
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+function %h() {
+block0:
+  debugtrap
+  return
+}
+
+; check: debugtrap