Support IBM z/Architecture
This adds support for the IBM z/Architecture (s390x-ibm-linux). The status of the s390x backend in its current form is: - Wasmtime is fully functional and passes all tests on s390x. - All back-end features supported, with the exception of SIMD. - There is still a lot of potential for performance improvements. - Currently the only supported processor type is z15.
This commit is contained in:
Ulrich Weigand
168
cranelift/codegen/src/isa/s390x/inst/regs.rs
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168
cranelift/codegen/src/isa/s390x/inst/regs.rs
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//! S390x ISA definitions: registers.
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use crate::settings;
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use regalloc::{RealRegUniverse, Reg, RegClass, RegClassInfo, Writable, NUM_REG_CLASSES};
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//=============================================================================
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// Registers, the Universe thereof, and printing
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#[rustfmt::skip]
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const GPR_INDICES: [u8; 16] = [
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// r0 and r1 reserved
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30, 31,
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// r2 - r5 call-clobbered
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16, 17, 18, 19,
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// r6 - r14 call-saved (order reversed)
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28, 27, 26, 25, 24, 23, 22, 21, 20,
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// r15 (SP)
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29,
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];
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#[rustfmt::skip]
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const FPR_INDICES: [u8; 16] = [
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// f0 - f7 as pairs
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0, 4, 1, 5, 2, 6, 3, 7,
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// f8 - f15 as pairs
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8, 12, 9, 13, 10, 14, 11, 15,
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];
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/// Get a reference to a GPR (integer register).
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pub fn gpr(num: u8) -> Reg {
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assert!(num < 16);
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Reg::new_real(
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RegClass::I64,
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/* enc = */ num,
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/* index = */ GPR_INDICES[num as usize],
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)
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}
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/// Get a writable reference to a GPR.
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pub fn writable_gpr(num: u8) -> Writable<Reg> {
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Writable::from_reg(gpr(num))
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}
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/// Get a reference to a FPR (floating-point register).
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pub fn fpr(num: u8) -> Reg {
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assert!(num < 16);
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Reg::new_real(
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RegClass::F64,
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/* enc = */ num,
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/* index = */ FPR_INDICES[num as usize],
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)
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}
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/// Get a writable reference to a V-register.
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pub fn writable_fpr(num: u8) -> Writable<Reg> {
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Writable::from_reg(fpr(num))
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}
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/// Get a reference to the stack-pointer register.
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pub fn stack_reg() -> Reg {
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gpr(15)
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}
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/// Get a writable reference to the stack-pointer register.
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pub fn writable_stack_reg() -> Writable<Reg> {
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Writable::from_reg(stack_reg())
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}
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/// Get a reference to the first temporary, sometimes "spill temporary", register. This register is
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/// used to compute the address of a spill slot when a direct offset addressing mode from FP is not
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/// sufficient (+/- 2^11 words). We exclude this register from regalloc and reserve it for this
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/// purpose for simplicity; otherwise we need a multi-stage analysis where we first determine how
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/// many spill slots we have, then perhaps remove the reg from the pool and recompute regalloc.
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///
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/// We use r1 for this because it's a scratch register but is slightly special (used for linker
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/// veneers). We're free to use it as long as we don't expect it to live through call instructions.
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pub fn spilltmp_reg() -> Reg {
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gpr(1)
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}
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/// Get a writable reference to the spilltmp reg.
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pub fn writable_spilltmp_reg() -> Writable<Reg> {
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Writable::from_reg(spilltmp_reg())
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}
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pub fn zero_reg() -> Reg {
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gpr(0)
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}
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/// Create the register universe for AArch64.
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pub fn create_reg_universe(_flags: &settings::Flags) -> RealRegUniverse {
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let mut regs = vec![];
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let mut allocable_by_class = [None; NUM_REG_CLASSES];
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// Numbering Scheme: we put FPRs first, then GPRs. The GPRs exclude several registers:
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// r0 (we cannot use this for addressing // FIXME regalloc)
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// r1 (spilltmp)
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// r15 (stack pointer)
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// FPRs.
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let mut base = regs.len();
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regs.push((fpr(0).to_real_reg(), "%f0".into()));
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regs.push((fpr(2).to_real_reg(), "%f2".into()));
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regs.push((fpr(4).to_real_reg(), "%f4".into()));
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regs.push((fpr(6).to_real_reg(), "%f6".into()));
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regs.push((fpr(1).to_real_reg(), "%f1".into()));
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regs.push((fpr(3).to_real_reg(), "%f3".into()));
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regs.push((fpr(5).to_real_reg(), "%f5".into()));
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regs.push((fpr(7).to_real_reg(), "%f7".into()));
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regs.push((fpr(8).to_real_reg(), "%f8".into()));
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regs.push((fpr(10).to_real_reg(), "%f10".into()));
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regs.push((fpr(12).to_real_reg(), "%f12".into()));
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regs.push((fpr(14).to_real_reg(), "%f14".into()));
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regs.push((fpr(9).to_real_reg(), "%f9".into()));
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regs.push((fpr(11).to_real_reg(), "%f11".into()));
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regs.push((fpr(13).to_real_reg(), "%f13".into()));
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regs.push((fpr(15).to_real_reg(), "%f15".into()));
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allocable_by_class[RegClass::F64.rc_to_usize()] = Some(RegClassInfo {
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first: base,
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last: regs.len() - 1,
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suggested_scratch: Some(fpr(1).get_index()),
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});
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// Caller-saved GPRs in the SystemV s390x ABI.
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base = regs.len();
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regs.push((gpr(2).to_real_reg(), "%r2".into()));
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regs.push((gpr(3).to_real_reg(), "%r3".into()));
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regs.push((gpr(4).to_real_reg(), "%r4".into()));
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regs.push((gpr(5).to_real_reg(), "%r5".into()));
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// Callee-saved GPRs in the SystemV s390x ABI.
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// We start from r14 downwards in an attempt to allow the
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// prolog to use as short a STMG as possible.
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regs.push((gpr(14).to_real_reg(), "%r14".into()));
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regs.push((gpr(13).to_real_reg(), "%r13".into()));
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regs.push((gpr(12).to_real_reg(), "%r12".into()));
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regs.push((gpr(11).to_real_reg(), "%r11".into()));
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regs.push((gpr(10).to_real_reg(), "%r10".into()));
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regs.push((gpr(9).to_real_reg(), "%r9".into()));
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regs.push((gpr(8).to_real_reg(), "%r8".into()));
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regs.push((gpr(7).to_real_reg(), "%r7".into()));
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regs.push((gpr(6).to_real_reg(), "%r6".into()));
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allocable_by_class[RegClass::I64.rc_to_usize()] = Some(RegClassInfo {
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first: base,
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last: regs.len() - 1,
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suggested_scratch: Some(gpr(13).get_index()),
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});
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// Other regs, not available to the allocator.
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let allocable = regs.len();
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regs.push((gpr(15).to_real_reg(), "%r15".into()));
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regs.push((gpr(0).to_real_reg(), "%r0".into()));
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regs.push((gpr(1).to_real_reg(), "%r1".into()));
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// Assert sanity: the indices in the register structs must match their
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// actual indices in the array.
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for (i, reg) in regs.iter().enumerate() {
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assert_eq!(i, reg.0.get_index());
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}
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RealRegUniverse {
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regs,
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allocable,
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allocable_by_class,
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}
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}
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