Rename ScalarType to LaneType.

The word "scalar" is a bit vague and tends to mean "non-vector". Since
we are about to add new CPU flag value types that can't appear as vector
lanes, make the distinction clear: LaneType represents value types that
can appear as a vector lane.

Also replace the Type::is_scalar() method with an is_vector() method.

lib/cretonne/src/abi.rs

@@ -164,21 +164,19 @@ pub fn legalize_abi_value(have: Type, arg: &ArgumentType) -> ValueConversion {
         Ordering::Equal => {
             // This must be an integer vector that is split and then extended.
             assert!(arg.value_type.is_int());
-            assert!(!have.is_scalar());
+            assert!(have.is_vector());
             ValueConversion::VectorSplit
         }
         // We have more bits than the argument.
         Ordering::Greater => {
-            if have.is_scalar() {
-                if have.is_float() {
-                    // Convert a float to int so it can be split the next time.
-                    // ARM would do this to pass an `f64` in two registers.
-                    ValueConversion::IntBits
-                } else {
-                    ValueConversion::IntSplit
-                }
-            } else {
+            if have.is_vector() {
                 ValueConversion::VectorSplit
+            } else if have.is_float() {
+                // Convert a float to int so it can be split the next time.
+                // ARM would do this to pass an `f64` in two registers.
+                ValueConversion::IntBits
+            } else {
+                ValueConversion::IntSplit
             }
         }
     }

lib/cretonne/src/ir/types.rs

@@ -38,7 +38,7 @@ include!(concat!(env!("OUT_DIR"), "/types.rs"));
 impl Type {
     /// Get the lane type of this SIMD vector type.
     ///
-    /// A scalar type is the same as a SIMD vector type with one lane, so it returns itself.
+    /// A lane type is the same as a SIMD vector type with one lane, so it returns itself.
     pub fn lane_type(self) -> Type {
         Type(self.0 & 0x0f)
     }
@@ -100,7 +100,7 @@ impl Type {
     ///
     /// Scalar types are all converted to `b1` which is usually what you want.
     pub fn as_bool(self) -> Type {
-        if self.is_scalar() {
+        if !self.is_vector() {
             B1
         } else {
             self.as_bool_pedantic()
@@ -173,16 +173,16 @@ impl Type {
     /// All SIMD types have a lane count that is a power of two and no larger than 256, so this
     /// will be a number in the range 0-8.
     ///
-    /// A scalar type is the same as a SIMD vector type with one lane, so it return 0.
+    /// A scalar type is the same as a SIMD vector type with one lane, so it returns 0.
     pub fn log2_lane_count(self) -> u8 {
         self.0 >> 4
     }
 
-    /// Is this a scalar type? (That is, not a SIMD vector type).
+    /// Is this a SIMD vector type?
     ///
-    /// A scalar type is the same as a SIMD vector type with one lane.
-    pub fn is_scalar(self) -> bool {
-        self.log2_lane_count() == 0
+    /// A vector type has 2 or more lanes.
+    pub fn is_vector(self) -> bool {
+        self.log2_lane_count() > 0
     }
 
     /// Get the number of lanes in this SIMD vector type.
@@ -225,10 +225,10 @@ impl Type {
     ///
     /// There is no `double_vector()` method. Use `t.by(2)` instead.
     pub fn half_vector(self) -> Option<Type> {
-        if self.is_scalar() {
-            None
-        } else {
+        if self.is_vector() {
             Some(Type(self.0 - 0x10))
+        } else {
+            None
         }
     }
 
@@ -255,7 +255,7 @@ impl Display for Type {
             write!(f, "i{}", self.lane_bits())
         } else if self.is_float() {
             write!(f, "f{}", self.lane_bits())
-        } else if !self.is_scalar() {
+        } else if self.is_vector() {
             write!(f, "{}x{}", self.lane_type(), self.lane_count())
         } else {
             panic!("Invalid Type(0x{:x})", self.0)
@@ -273,7 +273,7 @@ impl Debug for Type {
             write!(f, "types::I{}", self.lane_bits())
         } else if self.is_float() {
             write!(f, "types::F{}", self.lane_bits())
-        } else if !self.is_scalar() {
+        } else if self.is_vector() {
             write!(f, "{:?}X{}", self.lane_type(), self.lane_count())
         } else {
             write!(f, "Type(0x{:x})", self.0)

lib/cretonne/src/isa/intel/abi.rs

@@ -46,7 +46,7 @@ impl ArgAssigner for Args {
 
         // Check for a legal type.
         // We don't support SIMD yet, so break all vectors down.
-        if !ty.is_scalar() {
+        if ty.is_vector() {
             return ValueConversion::VectorSplit.into();
         }
 

lib/cretonne/src/isa/riscv/abi.rs

@@ -45,7 +45,7 @@ impl ArgAssigner for Args {
 
         // Check for a legal type.
         // RISC-V doesn't have SIMD at all, so break all vectors down.
-        if !ty.is_scalar() {
+        if ty.is_vector() {
             return ValueConversion::VectorSplit.into();
         }
 

lib/cretonne/src/legalizer/mod.rs

@@ -217,7 +217,7 @@ fn expand_select(inst: ir::Inst, func: &mut ir::Function, cfg: &mut ControlFlowG
 /// Expand illegal `f32const` and `f64const` instructions.
 fn expand_fconst(inst: ir::Inst, func: &mut ir::Function, _cfg: &mut ControlFlowGraph) {
     let ty = func.dfg.value_type(func.dfg.first_result(inst));
-    assert!(ty.is_scalar(), "Only scalar fconst supported: {}", ty);
+    assert!(!ty.is_vector(), "Only scalar fconst supported: {}", ty);
 
     // In the future, we may want to generate constant pool entries for these constants, but for
     // now use an `iconst` and a bit cast.