diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs
index 44b848edc5..97ad2abd95 100644
--- a/cranelift/codegen/src/isa/aarch64/abi.rs
+++ b/cranelift/codegen/src/isa/aarch64/abi.rs
@@ -619,7 +619,10 @@ impl ABIMachineSpec for AArch64MachineDeps {
         }
     }
 
-    fn gen_debug_frame_info(flags: &settings::Flags) -> SmallInstVec<Inst> {
+    fn gen_debug_frame_info(
+        flags: &settings::Flags,
+        _isa_flags: &Vec<settings::Value>,
+    ) -> SmallInstVec<Inst> {
         let mut insts = SmallVec::new();
         if flags.unwind_info() {
             insts.push(Inst::Unwind {
diff --git a/cranelift/codegen/src/isa/aarch64/mod.rs b/cranelift/codegen/src/isa/aarch64/mod.rs
index 16e45cba00..53159b0d0a 100644
--- a/cranelift/codegen/src/isa/aarch64/mod.rs
+++ b/cranelift/codegen/src/isa/aarch64/mod.rs
@@ -57,7 +57,7 @@ impl AArch64Backend {
         flags: shared_settings::Flags,
     ) -> CodegenResult<VCode<inst::Inst>> {
         let emit_info = EmitInfo::new(flags.clone());
-        let abi = Box::new(abi::AArch64ABICallee::new(func, flags)?);
+        let abi = Box::new(abi::AArch64ABICallee::new(func, flags, self.isa_flags())?);
         compile::compile::<AArch64Backend>(func, self, abi, &self.reg_universe, emit_info)
     }
 }
diff --git a/cranelift/codegen/src/isa/arm32/mod.rs b/cranelift/codegen/src/isa/arm32/mod.rs
index f6a5ba8267..f66809bfc9 100644
--- a/cranelift/codegen/src/isa/arm32/mod.rs
+++ b/cranelift/codegen/src/isa/arm32/mod.rs
@@ -48,7 +48,7 @@ impl Arm32Backend {
         // This performs lowering to VCode, register-allocates the code, computes
         // block layout and finalizes branches. The result is ready for binary emission.
         let emit_info = EmitInfo::new(flags.clone());
-        let abi = Box::new(abi::Arm32ABICallee::new(func, flags)?);
+        let abi = Box::new(abi::Arm32ABICallee::new(func, flags, self.isa_flags())?);
         compile::compile::<Arm32Backend>(func, self, abi, &self.reg_universe, emit_info)
     }
 }
diff --git a/cranelift/codegen/src/isa/s390x/mod.rs b/cranelift/codegen/src/isa/s390x/mod.rs
index 046e077fcd..6093cb1d9e 100644
--- a/cranelift/codegen/src/isa/s390x/mod.rs
+++ b/cranelift/codegen/src/isa/s390x/mod.rs
@@ -60,7 +60,7 @@ impl S390xBackend {
         flags: shared_settings::Flags,
     ) -> CodegenResult<VCode<inst::Inst>> {
         let emit_info = EmitInfo::new(flags.clone(), self.isa_flags.clone());
-        let abi = Box::new(abi::S390xABICallee::new(func, flags)?);
+        let abi = Box::new(abi::S390xABICallee::new(func, flags, self.isa_flags())?);
         compile::compile::<S390xBackend>(func, self, abi, &self.reg_universe, emit_info)
     }
 }
diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs
index 5fe00926a0..6c8782e9cc 100644
--- a/cranelift/codegen/src/isa/x64/mod.rs
+++ b/cranelift/codegen/src/isa/x64/mod.rs
@@ -49,7 +49,7 @@ impl X64Backend {
         // This performs lowering to VCode, register-allocates the code, computes
         // block layout and finalizes branches. The result is ready for binary emission.
         let emit_info = EmitInfo::new(flags.clone(), self.x64_flags.clone());
-        let abi = Box::new(abi::X64ABICallee::new(&func, flags)?);
+        let abi = Box::new(abi::X64ABICallee::new(&func, flags, self.isa_flags())?);
         compile::compile::<Self>(&func, self, abi, &self.reg_universe, emit_info)
     }
 }
diff --git a/cranelift/codegen/src/machinst/abi_impl.rs b/cranelift/codegen/src/machinst/abi_impl.rs
index 5126752db0..065ee7074c 100644
--- a/cranelift/codegen/src/machinst/abi_impl.rs
+++ b/cranelift/codegen/src/machinst/abi_impl.rs
@@ -419,7 +419,10 @@ pub trait ABIMachineSpec {
 
     /// Generates extra unwind instructions for a new frame  for this
     /// architecture, whether the frame has a prologue sequence or not.
-    fn gen_debug_frame_info(_flags: &settings::Flags) -> SmallInstVec<Self::I> {
+    fn gen_debug_frame_info(
+        _flags: &settings::Flags,
+        _isa_flags: &Vec<settings::Value>,
+    ) -> SmallInstVec<Self::I> {
         // By default, generates nothing.
         smallvec![]
     }
@@ -619,6 +622,8 @@ pub struct ABICalleeImpl<M: ABIMachineSpec> {
     call_conv: isa::CallConv,
     /// The settings controlling this function's compilation.
     flags: settings::Flags,
+    /// The ISA-specific flag values controlling this function's compilation.
+    isa_flags: Vec<settings::Value>,
     /// Whether or not this function is a "leaf", meaning it calls no other
     /// functions
     is_leaf: bool,
@@ -670,7 +675,11 @@ fn ty_from_class(class: RegClass) -> Type {
 
 impl<M: ABIMachineSpec> ABICalleeImpl<M> {
     /// Create a new body ABI instance.
-    pub fn new(f: &ir::Function, flags: settings::Flags) -> CodegenResult<Self> {
+    pub fn new(
+        f: &ir::Function,
+        flags: settings::Flags,
+        isa_flags: Vec<settings::Value>,
+    ) -> CodegenResult<Self> {
         log::trace!("ABI: func signature {:?}", f.signature);
 
         let ir_sig = ensure_struct_return_ptr_is_returned(&f.signature);
@@ -737,6 +746,7 @@ impl<M: ABIMachineSpec> ABICalleeImpl<M> {
             ret_area_ptr: None,
             call_conv,
             flags,
+            isa_flags,
             is_leaf: f.is_leaf(),
             stack_limit,
             probestack_min_frame,
@@ -1266,7 +1276,7 @@ impl<M: ABIMachineSpec> ABICallee for ABICalleeImpl<M> {
                 self.fixed_frame_storage_size,
             );
 
-            insts.extend(M::gen_debug_frame_info(&self.flags).into_iter());
+            insts.extend(M::gen_debug_frame_info(&self.flags, &self.isa_flags).into_iter());
 
             if self.setup_frame {
                 // set up frame