T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Replace as casts with type-conversion functions.

Browse Source
This commit is contained in:
Dan Gohman
2017-11-08 10:41:09 -08:00
parent 7c579a80c2
commit 889b06fd16
15 changed files with 54 additions and 47 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
lib/cretonne/src/entity/set.rs
View File

@@ -78,6 +78,7 @@ where
#[cfg(test)]
mod tests {
use super::*;
use std::u32;
// `EntityRef` impl for testing.
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
@@ -133,7 +134,7 @@ mod tests {
assert!(!m.contains(E(16)));
assert!(!m.contains(E(19)));
assert!(!m.contains(E(20)));
assert!(!m.contains(E(u32::max_value())));
assert!(!m.contains(E(u32::MAX)));
m.clear();
assert!(m.is_empty());

18
lib/cretonne/src/ir/immediates.rs
View File

@@ -163,7 +163,7 @@ impl Into<u32> for Uimm32 {
impl Into<i64> for Uimm32 {
fn into(self) -> i64 {
self.0 as i64
i64::from(self.0)
}
}
@@ -178,7 +178,7 @@ impl Display for Uimm32 {
if self.0 < 10_000 {
write!(f, "{}", self.0)
} else {
write_hex(self.0 as i64, f)
write_hex(i64::from(self.0), f)
}
}
@@ -189,7 +189,7 @@ impl FromStr for Uimm32 {
// Parse a decimal or hexadecimal `Uimm32`, formatted as above.
fn from_str(s: &str) -> Result<Uimm32, &'static str> {
parse_i64(s).and_then(|x| if 0 <= x && x <= u32::MAX as i64 {
parse_i64(s).and_then(|x| if 0 <= x && x <= i64::from(u32::MAX) {
Ok(Uimm32(x as u32))
} else {
Err("Uimm32 out of range")
@@ -439,7 +439,7 @@ fn parse_float(s: &str, w: u8, t: u8) -> Result<u64, &'static str> {
let exp_str = &s3[1 + idx..];
match exp_str.parse::<i16>() {
Ok(e) => {
exponent = e as i32;
exponent = i32::from(e);
break;
}
Err(_) => return Err("Bad exponent"),
@@ -473,7 +473,7 @@ fn parse_float(s: &str, w: u8, t: u8) -> Result<u64, &'static str> {
// Number of bits appearing after the radix point.
match digits_before_period {
None => {} // No radix point present.
Some(d) => exponent -= 4 * (digits - d) as i32,
Some(d) => exponent -= 4 * i32::from(digits - d),
};
// Normalize the significand and exponent.
@@ -485,11 +485,11 @@ fn parse_float(s: &str, w: u8, t: u8) -> Result<u64, &'static str> {
}
// Adjust significand down.
significand >>= adjust;
exponent += adjust as i32;
exponent += i32::from(adjust);
} else {
let adjust = t + 1 - significant_bits;
significand <<= adjust;
exponent -= adjust as i32;
exponent -= i32::from(adjust);
}
assert_eq!(significand >> t, 1);
@@ -498,7 +498,7 @@ fn parse_float(s: &str, w: u8, t: u8) -> Result<u64, &'static str> {
let max_exp = (1i32 << w) - 2;
let bias: i32 = (1 << (w - 1)) - 1;
exponent += bias + t as i32;
exponent += bias + i32::from(t);
if exponent > max_exp {
Err("Magnitude too large")
@@ -506,7 +506,7 @@ fn parse_float(s: &str, w: u8, t: u8) -> Result<u64, &'static str> {
// This is a normal number.
let e_bits = (exponent as u64) << t;
Ok(sign_bit | e_bits | t_bits)
} else if 1 - exponent <= t as i32 {
} else if 1 - exponent <= i32::from(t) {
// This is a subnormal number: e = 0, t = significand bits.
// Renormalize significand for exponent = 1.
let adjust = 1 - exponent;

3
lib/cretonne/src/isa/intel/abi.rs
View File

@@ -7,6 +7,7 @@ use settings as shared_settings;
use super::registers::{GPR, FPR, RU};
use abi::{ArgAction, ValueConversion, ArgAssigner, legalize_args};
use ir::{AbiParam, ArgumentPurpose, ArgumentLoc, ArgumentExtension};
use std::i32;
/// Argument registers for x86-64
static ARG_GPRS: [RU; 6] = [RU::rdi, RU::rsi, RU::rdx, RU::rcx, RU::r8, RU::r9];
@@ -99,7 +100,7 @@ impl ArgAssigner for Args {
// Assign a stack location.
let loc = ArgumentLoc::Stack(self.offset as i32);
self.offset += self.pointer_bytes;
assert!(self.offset <= i32::max_value() as u32);
assert!(self.offset <= i32::MAX as u32);
loc.into()
}
}

2
lib/cretonne/src/isa/intel/enc_tables.rs
View File

@@ -48,7 +48,7 @@ fn expand_srem(inst: ir::Inst, func: &mut ir::Function, cfg: &mut ControlFlowGra
// Now it is safe to execute the `x86_sdivmodx` instruction which will still trap on division
// by zero.
let xhi = pos.ins().sshr_imm(x, ty.lane_bits() as i64 - 1);
let xhi = pos.ins().sshr_imm(x, i64::from(ty.lane_bits()) - 1);
let (_qout, rem) = pos.ins().x86_sdivmodx(x, xhi, y);
pos.ins().jump(done, &[rem]);

2
lib/cretonne/src/isa/mod.rs
View File

@@ -244,7 +244,7 @@ pub trait TargetIsa {
// Account for the SpiderMonkey standard prologue pushes.
if func.signature.call_conv == ir::CallConv::SpiderWASM {
let bytes = self.flags().spiderwasm_prologue_words() as StackSize * word_size;
let bytes = StackSize::from(self.flags().spiderwasm_prologue_words()) * word_size;
let mut ss = ir::StackSlotData::new(ir::StackSlotKind::IncomingArg, bytes);
ss.offset = -(bytes as StackOffset);
func.stack_slots.push(ss);

4
lib/cretonne/src/isa/registers.rs
View File

@@ -253,8 +253,8 @@ impl fmt::Display for RegClassIndex {
/// A register is identified as a `(RegClass, RegUnit)` pair. The register class is needed to
/// determine the width (in regunits) of the register.
pub fn regs_overlap(rc1: RegClass, reg1: RegUnit, rc2: RegClass, reg2: RegUnit) -> bool {
let end1 = reg1 + rc1.width as RegUnit;
let end2 = reg2 + rc2.width as RegUnit;
let end1 = reg1 + RegUnit::from(rc1.width);
let end2 = reg2 + RegUnit::from(rc2.width);
!(end1 <= reg2 || end2 <= reg1)
}

3
lib/cretonne/src/isa/riscv/abi.rs
View File

@@ -12,6 +12,7 @@ use regalloc::AllocatableSet;
use settings as shared_settings;
use super::registers::{GPR, FPR};
use super::settings;
use std::i32;
struct Args {
pointer_bits: u16,
@@ -79,7 +80,7 @@ impl ArgAssigner for Args {
// Assign a stack location.
let loc = ArgumentLoc::Stack(self.offset as i32);
self.offset += self.pointer_bytes;
assert!(self.offset <= i32::max_value() as u32);
assert!(self.offset <= i32::MAX as u32);
loc.into()
}
}

33
lib/cretonne/src/isa/riscv/binemit.rs
View File

@@ -5,6 +5,7 @@ use ir::{Function, Inst, InstructionData};
use isa::{RegUnit, StackRef, StackBaseMask};
use predicates::is_signed_int;
use regalloc::RegDiversions;
use std::u32;
include!(concat!(env!("OUT_DIR"), "/binemit-riscv.rs"));
@@ -30,13 +31,13 @@ impl Into<Reloc> for RelocKind {
///
/// Encoding bits: `opcode[6:2] | (funct3 << 5) | (funct7 << 8)`.
fn put_r<CS: CodeSink + ?Sized>(bits: u16, rs1: RegUnit, rs2: RegUnit, rd: RegUnit, sink: &mut CS) {
let bits = bits as u32;
let bits = u32::from(bits);
let opcode5 = bits & 0x1f;
let funct3 = (bits >> 5) & 0x7;
let funct7 = (bits >> 8) & 0x7f;
let rs1 = rs1 as u32 & 0x1f;
let rs2 = rs2 as u32 & 0x1f;
let rd = rd as u32 & 0x1f;
let rs1 = u32::from(rs1) & 0x1f;
let rs2 = u32::from(rs2) & 0x1f;
let rd = u32::from(rd) & 0x1f;
// 0-6: opcode
let mut i = 0x3;
@@ -66,13 +67,13 @@ fn put_rshamt<CS: CodeSink + ?Sized>(
rd: RegUnit,
sink: &mut CS,
) {
let bits = bits as u32;
let bits = u32::from(bits);
let opcode5 = bits & 0x1f;
let funct3 = (bits >> 5) & 0x7;
let funct7 = (bits >> 8) & 0x7f;
let rs1 = rs1 as u32 & 0x1f;
let rs1 = u32::from(rs1) & 0x1f;
let shamt = shamt as u32 & 0x3f;
let rd = rd as u32 & 0x1f;
let rd = u32::from(rd) & 0x1f;
// 0-6: opcode
let mut i = 0x3;
@@ -94,11 +95,11 @@ fn put_rshamt<CS: CodeSink + ?Sized>(
///
/// Encoding bits: `opcode[6:2] | (funct3 << 5)`
fn put_i<CS: CodeSink + ?Sized>(bits: u16, rs1: RegUnit, imm: i64, rd: RegUnit, sink: &mut CS) {
let bits = bits as u32;
let bits = u32::from(bits);
let opcode5 = bits & 0x1f;
let funct3 = (bits >> 5) & 0x7;
let rs1 = rs1 as u32 & 0x1f;
let rd = rd as u32 & 0x1f;
let rs1 = u32::from(rs1) & 0x1f;
let rd = u32::from(rd) & 0x1f;
// 0-6: opcode
let mut i = 0x3;
@@ -121,7 +122,7 @@ fn put_i<CS: CodeSink + ?Sized>(bits: u16, rs1: RegUnit, imm: i64, rd: RegUnit,
fn put_u<CS: CodeSink + ?Sized>(bits: u16, imm: i64, rd: RegUnit, sink: &mut CS) {
let bits = bits as u32;
let opcode5 = bits & 0x1f;
let rd = rd as u32 & 0x1f;
let rd = u32::from(rd) & 0x1f;
// 0-6: opcode
let mut i = 0x3;
@@ -140,11 +141,11 @@ fn put_u<CS: CodeSink + ?Sized>(bits: u16, imm: i64, rd: RegUnit, sink: &mut CS)
///
/// Encoding bits: `opcode[6:2] | (funct3 << 5)`
fn put_sb<CS: CodeSink + ?Sized>(bits: u16, imm: i64, rs1: RegUnit, rs2: RegUnit, sink: &mut CS) {
let bits = bits as u32;
let bits = u32::from(bits);
let opcode5 = bits & 0x1f;
let funct3 = (bits >> 5) & 0x7;
let rs1 = rs1 as u32 & 0x1f;
let rs2 = rs2 as u32 & 0x1f;
let rs1 = u32::from(rs1) & 0x1f;
let rs2 = u32::from(rs2) & 0x1f;
assert!(is_signed_int(imm, 13, 1), "SB out of range {:#x}", imm);
let imm = imm as u32;
@@ -173,9 +174,9 @@ fn put_sb<CS: CodeSink + ?Sized>(bits: u16, imm: i64, rs1: RegUnit, rs2: RegUnit
///
/// Encoding bits: `opcode[6:2]`
fn put_uj<CS: CodeSink + ?Sized>(bits: u16, imm: i64, rd: RegUnit, sink: &mut CS) {
let bits = bits as u32;
let bits = u32::from(bits);
let opcode5 = bits & 0x1f;
let rd = rd as u32 & 0x1f;
let rd = u32::from(rd) & 0x1f;
assert!(is_signed_int(imm, 21, 1), "UJ out of range {:#x}", imm);
let imm = imm as u32;

4
lib/cretonne/src/legalizer/heap.rs
View File

@@ -43,7 +43,7 @@ fn dynamic_addr(
bound_gv: ir::GlobalVar,
func: &mut ir::Function,
) {
let size = size as i64;
let size = i64::from(size);
let offset_ty = func.dfg.value_type(offset);
let addr_ty = func.dfg.value_type(func.dfg.first_result(inst));
let min_size = func.heaps[heap].min_size.into();
@@ -96,7 +96,7 @@ fn static_addr(
bound: i64,
func: &mut ir::Function,
) {
let size = size as i64;
let size = i64::from(size);
let offset_ty = func.dfg.value_type(offset);
let addr_ty = func.dfg.value_type(func.dfg.first_result(inst));
let mut pos = FuncCursor::new(func).at_inst(inst);

2
lib/cretonne/src/legalizer/mod.rs
View File

@@ -227,7 +227,7 @@ fn expand_fconst(inst: ir::Inst, func: &mut ir::Function, _cfg: &mut ControlFlow
ir::InstructionData::UnaryIeee32 {
opcode: ir::Opcode::F32const,
imm,
} => pos.ins().iconst(ir::types::I32, imm.bits() as i64),
} => pos.ins().iconst(ir::types::I32, i64::from(imm.bits())),
ir::InstructionData::UnaryIeee64 {
opcode: ir::Opcode::F64const,
imm,

4
lib/cretonne/src/regalloc/allocatable_set.rs
View File

@@ -198,7 +198,9 @@ impl<'a> fmt::Display for DisplayAllocatableSet<'a> {
bank.names
.get(offset as usize)
.and_then(|name| name.chars().skip(1).next())
.unwrap_or(char::from_digit((offset % 10) as u32, 10).unwrap())
.unwrap_or(
char::from_digit(u32::from(offset % 10), 10).unwrap(),
)
)?;
}
}

4
lib/cretonne/src/regalloc/pressure.rs
View File

@@ -158,13 +158,13 @@ impl Pressure {
fn check_avail_aliased(&self, entry: &TopRC) -> RegClassMask {
let first = usize::from(entry.first_toprc);
let num = usize::from(entry.num_toprcs);
let width = entry.width as u32;
let width = u32::from(entry.width);
let ulimit = entry.limit * width;
// Count up the number of available register units.
let mut units = 0;
for (rc, rci) in self.toprc[first..first + num].iter().zip(first..) {
let rcw = rc.width as u32;
let rcw = u32::from(rc.width);
// If `rc.width` is smaller than `width`, each register in `rc` could potentially block
// one of ours. This is assuming that none of the smaller registers are straddling the
// bigger ones.

3
lib/cretonne/src/regalloc/solver.rs
View File

@@ -107,6 +107,7 @@ use std::cmp;
use std::fmt;
use std::mem;
use super::AllocatableSet;
use std::u16;
/// A variable in the constraint problem.
///
@@ -866,7 +867,7 @@ impl Solver {
// Compute domain sizes for all the variables given the current register sets.
for v in &mut self.vars {
let d = v.iter(&self.regs_in, &self.regs_out, global_regs).len();
v.domain = cmp::min(d, u16::max_value() as usize) as u16;
v.domain = cmp::min(d, u16::MAX as usize) as u16;
}
// Solve for vars with small domains first to increase the chance of finding a solution.
// Use the value number as a tie breaker to get a stable sort.

2
lib/reader/src/lexer.rs
View File

@@ -352,7 +352,7 @@ impl<'a> Lexer<'a> {
_ => return None,
};
if is_vector {
if number <= u16::MAX as u32 {
if number <= u32::from(u16::MAX) {
base_type.by(number as u16).map(Token::Type)
} else {
None

14
lib/wasm/src/code_translator.rs
View File

@@ -32,7 +32,7 @@ use translation_utils::{TableIndex, SignatureIndex, FunctionIndex, MemoryIndex};
use state::{TranslationState, ControlStackFrame};
use std::collections::{HashMap, hash_map};
use environ::{FuncEnvironment, GlobalValue};
use std::u32;
use std::{i32, u32};
/// Translates wasm operators into Cretonne IL instructions. Returns `true` if it inserted
/// a return.
@@ -477,7 +477,7 @@ pub fn translate_operator<FE: FuncEnvironment + ?Sized>(
translate_store(offset, ir::Opcode::Istore32, builder, state, environ);
}
/****************************** Nullary Operators ************************************/
Operator::I32Const { value } => state.push1(builder.ins().iconst(I32, value as i64)),
Operator::I32Const { value } => state.push1(builder.ins().iconst(I32, i64::from(value))),
Operator::I64Const { value } => state.push1(builder.ins().iconst(I64, value)),
Operator::F32Const { value } => {
state.push1(builder.ins().f32const(f32_translation(value)));
@@ -924,17 +924,17 @@ fn get_heap_addr(
// even if the access goes beyond the guard pages. This is because the first byte pointed to is
// inside the guard pages.
let check_size = min(
u32::max_value() as i64,
1 + (offset as i64 / guard_size) * guard_size,
i64::from(u32::MAX),
1 + (i64::from(offset) / guard_size) * guard_size,
) as u32;
let base = builder.ins().heap_addr(addr_ty, heap, addr32, check_size);
// Native load/store instructions take a signed `Offset32` immediate, so adjust the base
// pointer if necessary.
if offset > i32::max_value() as u32 {
if offset > i32::MAX as u32 {
// Offset doesn't fit in the load/store instruction.
let adj = builder.ins().iadd_imm(base, i32::max_value() as i64 + 1);
(adj, (offset - (i32::max_value() as u32 + 1)) as i32)
let adj = builder.ins().iadd_imm(base, i64::from(i32::MAX) + 1);
(adj, (offset - (i32::MAX as u32 + 1)) as i32)
} else {
(base, offset as i32)
}