Replace as casts with type-conversion functions.

lib/cretonne/src/isa/intel/abi.rs

@@ -7,6 +7,7 @@ use settings as shared_settings;
 use super::registers::{GPR, FPR, RU};
 use abi::{ArgAction, ValueConversion, ArgAssigner, legalize_args};
 use ir::{AbiParam, ArgumentPurpose, ArgumentLoc, ArgumentExtension};
+use std::i32;
 
 /// Argument registers for x86-64
 static ARG_GPRS: [RU; 6] = [RU::rdi, RU::rsi, RU::rdx, RU::rcx, RU::r8, RU::r9];
@@ -99,7 +100,7 @@ impl ArgAssigner for Args {
         // Assign a stack location.
         let loc = ArgumentLoc::Stack(self.offset as i32);
         self.offset += self.pointer_bytes;
-        assert!(self.offset <= i32::max_value() as u32);
+        assert!(self.offset <= i32::MAX as u32);
         loc.into()
     }
 }

lib/cretonne/src/isa/intel/enc_tables.rs

@@ -48,7 +48,7 @@ fn expand_srem(inst: ir::Inst, func: &mut ir::Function, cfg: &mut ControlFlowGra
 
     // Now it is safe to execute the `x86_sdivmodx` instruction which will still trap on division
     // by zero.
-    let xhi = pos.ins().sshr_imm(x, ty.lane_bits() as i64 - 1);
+    let xhi = pos.ins().sshr_imm(x, i64::from(ty.lane_bits()) - 1);
     let (_qout, rem) = pos.ins().x86_sdivmodx(x, xhi, y);
     pos.ins().jump(done, &[rem]);