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Replace as casts with type-conversion functions.

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This commit is contained in:
Dan Gohman
2017-11-08 10:41:09 -08:00
parent 7c579a80c2
commit 889b06fd16
15 changed files with 54 additions and 47 deletions
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3
lib/cretonne/src/isa/intel/abi.rs
View File

@@ -7,6 +7,7 @@ use settings as shared_settings;
use super::registers::{GPR, FPR, RU};
use abi::{ArgAction, ValueConversion, ArgAssigner, legalize_args};
use ir::{AbiParam, ArgumentPurpose, ArgumentLoc, ArgumentExtension};
use std::i32;
/// Argument registers for x86-64
static ARG_GPRS: [RU; 6] = [RU::rdi, RU::rsi, RU::rdx, RU::rcx, RU::r8, RU::r9];
@@ -99,7 +100,7 @@ impl ArgAssigner for Args {
// Assign a stack location.
let loc = ArgumentLoc::Stack(self.offset as i32);
self.offset += self.pointer_bytes;
assert!(self.offset <= i32::max_value() as u32);
assert!(self.offset <= i32::MAX as u32);
loc.into()
}
}

2
lib/cretonne/src/isa/intel/enc_tables.rs
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@@ -48,7 +48,7 @@ fn expand_srem(inst: ir::Inst, func: &mut ir::Function, cfg: &mut ControlFlowGra
// Now it is safe to execute the `x86_sdivmodx` instruction which will still trap on division
// by zero.
let xhi = pos.ins().sshr_imm(x, ty.lane_bits() as i64 - 1);
let xhi = pos.ins().sshr_imm(x, i64::from(ty.lane_bits()) - 1);
let (_qout, rem) = pos.ins().x86_sdivmodx(x, xhi, y);
pos.ins().jump(done, &[rem]);

2
lib/cretonne/src/isa/mod.rs
View File

@@ -244,7 +244,7 @@ pub trait TargetIsa {
// Account for the SpiderMonkey standard prologue pushes.
if func.signature.call_conv == ir::CallConv::SpiderWASM {
let bytes = self.flags().spiderwasm_prologue_words() as StackSize * word_size;
let bytes = StackSize::from(self.flags().spiderwasm_prologue_words()) * word_size;
let mut ss = ir::StackSlotData::new(ir::StackSlotKind::IncomingArg, bytes);
ss.offset = -(bytes as StackOffset);
func.stack_slots.push(ss);

4
lib/cretonne/src/isa/registers.rs
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@@ -253,8 +253,8 @@ impl fmt::Display for RegClassIndex {
/// A register is identified as a `(RegClass, RegUnit)` pair. The register class is needed to
/// determine the width (in regunits) of the register.
pub fn regs_overlap(rc1: RegClass, reg1: RegUnit, rc2: RegClass, reg2: RegUnit) -> bool {
let end1 = reg1 + rc1.width as RegUnit;
let end2 = reg2 + rc2.width as RegUnit;
let end1 = reg1 + RegUnit::from(rc1.width);
let end2 = reg2 + RegUnit::from(rc2.width);
!(end1 <= reg2 || end2 <= reg1)
}

3
lib/cretonne/src/isa/riscv/abi.rs
View File

@@ -12,6 +12,7 @@ use regalloc::AllocatableSet;
use settings as shared_settings;
use super::registers::{GPR, FPR};
use super::settings;
use std::i32;
struct Args {
pointer_bits: u16,
@@ -79,7 +80,7 @@ impl ArgAssigner for Args {
// Assign a stack location.
let loc = ArgumentLoc::Stack(self.offset as i32);
self.offset += self.pointer_bytes;
assert!(self.offset <= i32::max_value() as u32);
assert!(self.offset <= i32::MAX as u32);
loc.into()
}
}

33
lib/cretonne/src/isa/riscv/binemit.rs
View File

@@ -5,6 +5,7 @@ use ir::{Function, Inst, InstructionData};
use isa::{RegUnit, StackRef, StackBaseMask};
use predicates::is_signed_int;
use regalloc::RegDiversions;
use std::u32;
include!(concat!(env!("OUT_DIR"), "/binemit-riscv.rs"));
@@ -30,13 +31,13 @@ impl Into<Reloc> for RelocKind {
///
/// Encoding bits: `opcode[6:2] | (funct3 << 5) | (funct7 << 8)`.
fn put_r<CS: CodeSink + ?Sized>(bits: u16, rs1: RegUnit, rs2: RegUnit, rd: RegUnit, sink: &mut CS) {
let bits = bits as u32;
let bits = u32::from(bits);
let opcode5 = bits & 0x1f;
let funct3 = (bits >> 5) & 0x7;
let funct7 = (bits >> 8) & 0x7f;
let rs1 = rs1 as u32 & 0x1f;
let rs2 = rs2 as u32 & 0x1f;
let rd = rd as u32 & 0x1f;
let rs1 = u32::from(rs1) & 0x1f;
let rs2 = u32::from(rs2) & 0x1f;
let rd = u32::from(rd) & 0x1f;
// 0-6: opcode
let mut i = 0x3;
@@ -66,13 +67,13 @@ fn put_rshamt<CS: CodeSink + ?Sized>(
rd: RegUnit,
sink: &mut CS,
) {
let bits = bits as u32;
let bits = u32::from(bits);
let opcode5 = bits & 0x1f;
let funct3 = (bits >> 5) & 0x7;
let funct7 = (bits >> 8) & 0x7f;
let rs1 = rs1 as u32 & 0x1f;
let rs1 = u32::from(rs1) & 0x1f;
let shamt = shamt as u32 & 0x3f;
let rd = rd as u32 & 0x1f;
let rd = u32::from(rd) & 0x1f;
// 0-6: opcode
let mut i = 0x3;
@@ -94,11 +95,11 @@ fn put_rshamt<CS: CodeSink + ?Sized>(
///
/// Encoding bits: `opcode[6:2] | (funct3 << 5)`
fn put_i<CS: CodeSink + ?Sized>(bits: u16, rs1: RegUnit, imm: i64, rd: RegUnit, sink: &mut CS) {
let bits = bits as u32;
let bits = u32::from(bits);
let opcode5 = bits & 0x1f;
let funct3 = (bits >> 5) & 0x7;
let rs1 = rs1 as u32 & 0x1f;
let rd = rd as u32 & 0x1f;
let rs1 = u32::from(rs1) & 0x1f;
let rd = u32::from(rd) & 0x1f;
// 0-6: opcode
let mut i = 0x3;
@@ -121,7 +122,7 @@ fn put_i<CS: CodeSink + ?Sized>(bits: u16, rs1: RegUnit, imm: i64, rd: RegUnit,
fn put_u<CS: CodeSink + ?Sized>(bits: u16, imm: i64, rd: RegUnit, sink: &mut CS) {
let bits = bits as u32;
let opcode5 = bits & 0x1f;
let rd = rd as u32 & 0x1f;
let rd = u32::from(rd) & 0x1f;
// 0-6: opcode
let mut i = 0x3;
@@ -140,11 +141,11 @@ fn put_u<CS: CodeSink + ?Sized>(bits: u16, imm: i64, rd: RegUnit, sink: &mut CS)
///
/// Encoding bits: `opcode[6:2] | (funct3 << 5)`
fn put_sb<CS: CodeSink + ?Sized>(bits: u16, imm: i64, rs1: RegUnit, rs2: RegUnit, sink: &mut CS) {
let bits = bits as u32;
let bits = u32::from(bits);
let opcode5 = bits & 0x1f;
let funct3 = (bits >> 5) & 0x7;
let rs1 = rs1 as u32 & 0x1f;
let rs2 = rs2 as u32 & 0x1f;
let rs1 = u32::from(rs1) & 0x1f;
let rs2 = u32::from(rs2) & 0x1f;
assert!(is_signed_int(imm, 13, 1), "SB out of range {:#x}", imm);
let imm = imm as u32;
@@ -173,9 +174,9 @@ fn put_sb<CS: CodeSink + ?Sized>(bits: u16, imm: i64, rs1: RegUnit, rs2: RegUnit
///
/// Encoding bits: `opcode[6:2]`
fn put_uj<CS: CodeSink + ?Sized>(bits: u16, imm: i64, rd: RegUnit, sink: &mut CS) {
let bits = bits as u32;
let bits = u32::from(bits);
let opcode5 = bits & 0x1f;
let rd = rd as u32 & 0x1f;
let rd = u32::from(rd) & 0x1f;
assert!(is_signed_int(imm, 21, 1), "UJ out of range {:#x}", imm);
let imm = imm as u32;