From 880e692fd426ea2f46ebbc44a0d2a061cd16e910 Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 21 May 2020 22:09:25 +0000 Subject: [PATCH] x86: add encoding for bnot.b1. Fixes #1743. Co-authored-by: iximeow --- cranelift/codegen/meta/src/isa/x86/encodings.rs | 1 + cranelift/filetests/filetests/isa/x86/bnot-b1.clif | 14 ++++++++++++++ 2 files changed, 15 insertions(+) create mode 100644 cranelift/filetests/filetests/isa/x86/bnot-b1.clif diff --git a/cranelift/codegen/meta/src/isa/x86/encodings.rs b/cranelift/codegen/meta/src/isa/x86/encodings.rs index 7863e2bd85..9f1517253f 100644 --- a/cranelift/codegen/meta/src/isa/x86/encodings.rs +++ b/cranelift/codegen/meta/src/isa/x86/encodings.rs @@ -1454,6 +1454,7 @@ fn define_alu( // x86 has a bitwise not instruction NOT. e.enc_i32_i64(bnot, rec_ur.opcodes(&NOT).rrr(2)); e.enc_b32_b64(bnot, rec_ur.opcodes(&NOT).rrr(2)); + e.enc_both(bnot.bind(B1), rec_ur.opcodes(&NOT).rrr(2)); // Also add a `b1` encodings for the logic instructions. // TODO: Should this be done with 8-bit instructions? It would improve partial register diff --git a/cranelift/filetests/filetests/isa/x86/bnot-b1.clif b/cranelift/filetests/filetests/isa/x86/bnot-b1.clif new file mode 100644 index 0000000000..ef3736c54c --- /dev/null +++ b/cranelift/filetests/filetests/isa/x86/bnot-b1.clif @@ -0,0 +1,14 @@ +test binemit +test run + +target x86_64 + +function u0:323() -> b1 { +block0: + [-,%rax] v221 = bconst.b1 false ; bin: 40 b8 00000000 + [-,%rcx] v222 = bconst.b1 true ; bin: 40 b9 00000001 + [-,%rax] v223 = bnot v221 ; bin: 40 f7 d0 + [-,%rax] v224 = band v223, v222 ; bin: 40 21 c8 + return v224 +} +; run