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Add long-range encodings for conditional branches.

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The brz and brnz instructions get support for 32-bit jump displacements
for long range branches.

Also change the way branch ranges are specified on tail recipes for the
Intel instructions. All branch displacements are relative to the end of
the instruction, so just compute the branch range origin as the
instruction size instead of trying to specify it in the tail recipe
definitions.
This commit is contained in:
Jakob Stoklund Olesen
2017-09-29 13:18:29 -07:00
parent 50ccd000a9
commit 86e22e7de5
2 changed files with 56 additions and 16 deletions
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14
lib/cretonne/meta/isa/intel/encodings.py
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@@ -298,18 +298,18 @@ I32.enc(base.jump, *r.jmpd(0xe9))
I64.enc(base.jump, *r.jmpb(0xeb))
I64.enc(base.jump, *r.jmpd(0xe9))
# Note that the tjccd opcode will be prefixed with 0x0f.
enc_i32_i64(base.brz, r.tjccb, 0x74)
enc_i32_i64(base.brz, r.tjccd, 0x84)
enc_i32_i64(base.brnz, r.tjccb, 0x75)
enc_i32_i64(base.brnz, r.tjccd, 0x85)
# Branch on a b1 value in a register only looks at the low 8 bits. See also
# bint encodings below.
I32.enc(base.brz.b1, *r.t8jccb_abcd(0x74))
I64.enc(base.brz.b1, *r.t8jccb_abcd.rex(0x74))
I64.enc(base.brz.b1, *r.t8jccb_abcd(0x74))
I32.enc(base.brnz.b1, *r.t8jccb_abcd(0x75))
I64.enc(base.brnz.b1, *r.t8jccb_abcd.rex(0x75))
I64.enc(base.brnz.b1, *r.t8jccb_abcd(0x75))
enc_flt(base.brz.b1, r.t8jccb_abcd, 0x74)
enc_flt(base.brz.b1, r.t8jccd_abcd, 0x84)
enc_flt(base.brnz.b1, r.t8jccb_abcd, 0x75)
enc_flt(base.brnz.b1, r.t8jccd_abcd, 0x85)
#
# Trap as ud2