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cranelift: Fix icmp.i128 eq for aarch64 (#4706)

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* cranelift: Fix `icmp.i128 eq` for aarch64

* cranelift: Use ccmp in `icmp.i128 eq` for aarch64
This commit is contained in:
Afonso Bordado
2022-08-15 19:11:22 +01:00
committed by GitHub
parent e577a76c0d
commit 863cbc345c
7 changed files with 86 additions and 28 deletions
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20
cranelift/codegen/src/isa/aarch64/inst/emit.rs
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@@ -353,6 +353,15 @@ fn enc_fcsel(rd: Writable<Reg>, rn: Reg, rm: Reg, cond: Cond, size: ScalarSize)
| (cond.bits() << 12)
}
fn enc_ccmp(size: OperandSize, rn: Reg, rm: Reg, nzcv: NZCV, cond: Cond) -> u32 {
0b0_1_1_11010010_00000_0000_00_00000_0_0000
| size.sf_bit() << 31
| machreg_to_gpr(rm) << 16
| cond.bits() << 12
| machreg_to_gpr(rn) << 5
| nzcv.bits()
}
fn enc_ccmp_imm(size: OperandSize, rn: Reg, imm: UImm5, nzcv: NZCV, cond: Cond) -> u32 {
0b0_1_1_11010010_00000_0000_10_00000_0_0000
| size.sf_bit() << 31
@@ -1367,6 +1376,17 @@ impl MachInstEmit for Inst {
let rd = allocs.next_writable(rd);
sink.put4(enc_csel(rd, zero_reg(), zero_reg(), cond.invert(), 1, 0));
}
&Inst::CCmp {
size,
rn,
rm,
nzcv,
cond,
} => {
let rn = allocs.next(rn);
let rm = allocs.next(rm);
sink.put4(enc_ccmp(size, rn, rm, nzcv, cond));
}
&Inst::CCmpImm {
size,
rn,