From 85ec11acb921738f3515d23b9480e12e61a1bbaf Mon Sep 17 00:00:00 2001
From: Benjamin Bouvier <public@benj.me>
Date: Wed, 1 Sep 2021 17:53:14 +0200
Subject: [PATCH] Aarch64: always generate the CFA directive indicating no
 pointer signing

---
 cranelift/codegen/src/isa/aarch64/abi.rs                 | 8 ++++++--
 cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs | 5 ++++-
 cranelift/codegen/src/machinst/abi_impl.rs               | 9 +++++++++
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs
index 46eabe5de5..2a869185d4 100644
--- a/cranelift/codegen/src/isa/aarch64/abi.rs
+++ b/cranelift/codegen/src/isa/aarch64/abi.rs
@@ -619,9 +619,8 @@ impl ABIMachineSpec for AArch64MachineDeps {
         }
     }
 
-    fn gen_prologue_frame_setup(flags: &settings::Flags) -> SmallInstVec<Inst> {
+    fn gen_debug_frame_info(flags: &settings::Flags) -> SmallInstVec<Inst> {
         let mut insts = SmallVec::new();
-
         if flags.unwind_info() {
             insts.push(Inst::Unwind {
                 inst: UnwindInst::Aarch64SetPointerAuth {
@@ -629,6 +628,11 @@ impl ABIMachineSpec for AArch64MachineDeps {
                 },
             });
         }
+        insts
+    }
+
+    fn gen_prologue_frame_setup(flags: &settings::Flags) -> SmallInstVec<Inst> {
+        let mut insts = SmallVec::new();
 
         // stp fp (x29), lr (x30), [sp, #-16]!
         insts.push(Inst::StoreP64 {
diff --git a/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs b/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs
index 8f7edda09c..ade3767789 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/unwind/systemv.rs
@@ -143,7 +143,10 @@ mod tests {
             _ => panic!("expected unwind information"),
         };
 
-        assert_eq!(format!("{:?}", fde), "FrameDescriptionEntry { address: Constant(4321), length: 16, lsda: None, instructions: [] }");
+        assert_eq!(
+            format!("{:?}", fde),
+            "FrameDescriptionEntry { address: Constant(4321), length: 16, lsda: None, instructions: [(0, ValExpression(Register(34), Expression { operations: [Simple(DwOp(48))] }))] }"
+        );
     }
 
     fn create_multi_return_function(call_conv: CallConv) -> Function {
diff --git a/cranelift/codegen/src/machinst/abi_impl.rs b/cranelift/codegen/src/machinst/abi_impl.rs
index db37a5f81b..0da169b42c 100644
--- a/cranelift/codegen/src/machinst/abi_impl.rs
+++ b/cranelift/codegen/src/machinst/abi_impl.rs
@@ -417,6 +417,13 @@ pub trait ABIMachineSpec {
     /// Generate a meta-instruction that adjusts the nominal SP offset.
     fn gen_nominal_sp_adj(amount: i32) -> Self::I;
 
+    /// Generates extra unwind instructions for a new frame  for this
+    /// architecture, whether the frame has a prologue sequence or not.
+    fn gen_debug_frame_info(_flags: &settings::Flags) -> SmallInstVec<Self::I> {
+        // By default, generates nothing.
+        smallvec![]
+    }
+
     /// Generate the usual frame-setup sequence for this architecture: e.g.,
     /// `push rbp / mov rbp, rsp` on x86-64, or `stp fp, lr, [sp, #-16]!` on
     /// AArch64.
@@ -1289,6 +1296,8 @@ impl<M: ABIMachineSpec> ABICallee for ABICalleeImpl<M> {
                 self.fixed_frame_storage_size,
             );
 
+            insts.extend(M::gen_debug_frame_info(&self.flags).into_iter());
+
             if self.setup_frame {
                 // set up frame
                 insts.extend(M::gen_prologue_frame_setup(&self.flags).into_iter());