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Remove FPR32; fixes #1303

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Until #1306 is resolved (some spilling/regalloc issue with larger FPR register banks), this removes FPR32 support. Only Wasm's `i64x2.mul` was using this register class and that instruction is predicated on AVX512 support; for the time being, that instruction will have to make do with the 16 FPR registers.
This commit is contained in:
Andrew Brown
2020-03-13 14:54:23 -07:00
parent af709ded94
commit 8598295bc4
6 changed files with 34 additions and 35 deletions
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18
cranelift/codegen/meta/src/isa/x86/recipes.rs
View File

@@ -143,19 +143,18 @@ fn replace_nonrex_constraints(
}
fn replace_evex_constraints(
regs: &IsaRegs,
_: &IsaRegs,
constraints: Vec<OperandConstraint>,
) -> Vec<OperandConstraint> {
constraints
.into_iter()
.map(|constraint| match constraint {
OperandConstraint::RegClass(rc_index) => {
let new_rc_index = if rc_index == regs.class_by_name("FPR") {
regs.class_by_name("FPR32")
} else {
rc_index
};
OperandConstraint::RegClass(new_rc_index)
// FIXME(#1306) this should be able to upgrade the register class to FPR32 as in
// `replace_nonrex_constraints` above, e.g. When FPR32 is re-added, add back in the
// rc_index conversion to FPR32. In the meantime, this is effectively a no-op
// conversion--the register class stays the same.
OperandConstraint::RegClass(rc_index)
}
_ => constraint,
})
@@ -419,7 +418,6 @@ pub(crate) fn define<'shared>(
let abcd = regs.class_by_name("ABCD");
let gpr = regs.class_by_name("GPR");
let fpr = regs.class_by_name("FPR");
let fpr32 = regs.class_by_name("FPR32");
let flag = regs.class_by_name("FLAG");
// Operand constraints shorthands.
@@ -3364,8 +3362,8 @@ pub(crate) fn define<'shared>(
recipes.add_template(
Template::new(
EncodingRecipeBuilder::new("evex_reg_vvvv_rm_128", &formats.binary, 1)
.operands_in(vec![fpr32, fpr32])
.operands_out(vec![fpr32])
.operands_in(vec![fpr, fpr])
.operands_out(vec![fpr])
.emit(
r#"
// instruction encoding operands: reg (op1, w), vvvv (op2, r), rm (op3, r)

7
cranelift/codegen/meta/src/isa/x86/registers.rs
View File

@@ -4,7 +4,7 @@ pub(crate) fn define() -> IsaRegs {
let mut regs = IsaRegsBuilder::new();
let builder = RegBankBuilder::new("FloatRegs", "xmm")
.units(32)
.units(16)
.track_pressure(true);
let float_regs = regs.add_bank(builder);
@@ -24,10 +24,7 @@ pub(crate) fn define() -> IsaRegs {
let builder = RegClassBuilder::new_toplevel("GPR", int_regs);
let gpr = regs.add_class(builder);
let builder = RegClassBuilder::new_toplevel("FPR32", float_regs);
let fpr32 = regs.add_class(builder);
let builder = RegClassBuilder::subclass_of("FPR", fpr32, 0, 16);
let builder = RegClassBuilder::new_toplevel("FPR", float_regs);
let fpr = regs.add_class(builder);
let builder = RegClassBuilder::new_toplevel("FLAG", flag_reg);

22
cranelift/codegen/src/isa/x86/registers.rs
View File

@@ -33,11 +33,12 @@ mod tests {
assert_eq!(INFO.parse_regunit("xmm0"), fpr(0));
assert_eq!(INFO.parse_regunit("xmm15"), fpr(15));
fn fpr32(unit: usize) -> Option<u16> {
Some(FPR32.unit(unit))
}
assert_eq!(INFO.parse_regunit("xmm0"), fpr32(0));
assert_eq!(INFO.parse_regunit("xmm31"), fpr32(31));
// FIXME(#1306) Add these tests back in when FPR32 is re-added.
// fn fpr32(unit: usize) -> Option<u16> {
// Some(FPR32.unit(unit))
// }
// assert_eq!(INFO.parse_regunit("xmm0"), fpr32(0));
// assert_eq!(INFO.parse_regunit("xmm31"), fpr32(31));
}
#[test]
@@ -62,11 +63,12 @@ mod tests {
assert_eq!(fpr(0), "%xmm0");
assert_eq!(fpr(15), "%xmm15");
fn fpr32(ru: RegUnit) -> String {
INFO.display_regunit(FPR32.first + ru).to_string()
}
assert_eq!(fpr32(0), "%xmm0");
assert_eq!(fpr32(31), "%xmm31");
// FIXME(#1306) Add these tests back in when FPR32 is re-added.
// fn fpr32(ru: RegUnit) -> String {
// INFO.display_regunit(FPR32.first + ru).to_string()
// }
// assert_eq!(fpr32(0), "%xmm0");
// assert_eq!(fpr32(31), "%xmm31");
}
#[test]