From 850896f05e4ef04230b513440b05b9e3f29569d8 Mon Sep 17 00:00:00 2001
From: Tyler McMullen <tyler@fastly.com>
Date: Thu, 18 Jan 2018 13:36:15 -0800
Subject: [PATCH] The addend for a PLTRel4 reloc should be -4.

---
 lib/cretonne/meta/isa/intel/recipes.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/cretonne/meta/isa/intel/recipes.py b/lib/cretonne/meta/isa/intel/recipes.py
index e9c896123b..e613e9aeeb 100644
--- a/lib/cretonne/meta/isa/intel/recipes.py
+++ b/lib/cretonne/meta/isa/intel/recipes.py
@@ -899,7 +899,7 @@ call_plt_id = TailRecipe(
         PUT_OP(bits, BASE_REX, sink);
         sink.reloc_external(Reloc::IntelPLTRel4,
                             &func.dfg.ext_funcs[func_ref].name,
-                            0);
+                            -4);
         sink.put4(0);
         ''')