diff --git a/.travis.yml b/.travis.yml
index 0fe74d37d2..9329904a88 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -17,7 +17,8 @@ before_install:
     - wget https://storage.googleapis.com/wasm-llvm/builds/linux/26619/wasm-toolchain_0.1.26619_amd64.deb
     - sudo dpkg -i wasm-toolchain_0.1.26619_amd64.deb
 install:
-    - pip3 install --user --upgrade mypy==0.521 flake8
+    - pip3 install --user --upgrade mypy flake8
+    - mypy --version
     - travis_wait ./check-rustfmt.sh --install
 script: ./test-all.sh
 cache:
diff --git a/lib/codegen/meta/isa/arm32/__init__.py b/lib/codegen/meta/isa/arm32/__init__.py
index 9e0ae5a7e1..06773f8754 100644
--- a/lib/codegen/meta/isa/arm32/__init__.py
+++ b/lib/codegen/meta/isa/arm32/__init__.py
@@ -9,6 +9,7 @@ This target ISA generates code for ARMv7 and ARMv8 CPUs in 32-bit mode
 from __future__ import absolute_import
 from . import defs
 from . import settings, registers  # noqa
+from cdsl.isa import TargetISA  # noqa
 
 # Re-export the primary target ISA definition.
-ISA = defs.ISA.finish()
+ISA = defs.ISA.finish()  # type: TargetISA
diff --git a/lib/codegen/meta/isa/arm32/defs.py b/lib/codegen/meta/isa/arm32/defs.py
index 6bba598d27..88b8c53db4 100644
--- a/lib/codegen/meta/isa/arm32/defs.py
+++ b/lib/codegen/meta/isa/arm32/defs.py
@@ -8,7 +8,7 @@ from cdsl.isa import TargetISA, CPUMode
 import base.instructions
 from base.legalize import narrow
 
-ISA = TargetISA('arm32', [base.instructions.GROUP])
+ISA = TargetISA('arm32', [base.instructions.GROUP])  # type: TargetISA
 
 # CPU modes for 32-bit ARM and Thumb2.
 A32 = CPUMode('A32', ISA)
diff --git a/lib/codegen/meta/isa/arm64/__init__.py b/lib/codegen/meta/isa/arm64/__init__.py
index 3dd69feb4b..fb9005c037 100644
--- a/lib/codegen/meta/isa/arm64/__init__.py
+++ b/lib/codegen/meta/isa/arm64/__init__.py
@@ -8,6 +8,7 @@ ARMv8 CPUs running the Aarch64 architecture.
 from __future__ import absolute_import
 from . import defs
 from . import settings, registers  # noqa
+from cdsl.isa import TargetISA  # noqa
 
 # Re-export the primary target ISA definition.
-ISA = defs.ISA.finish()
+ISA = defs.ISA.finish()  # type: TargetISA
diff --git a/lib/codegen/meta/isa/arm64/defs.py b/lib/codegen/meta/isa/arm64/defs.py
index b1ed79b5d6..0350908f9b 100644
--- a/lib/codegen/meta/isa/arm64/defs.py
+++ b/lib/codegen/meta/isa/arm64/defs.py
@@ -8,7 +8,7 @@ from cdsl.isa import TargetISA, CPUMode
 import base.instructions
 from base.legalize import narrow
 
-ISA = TargetISA('arm64', [base.instructions.GROUP])
+ISA = TargetISA('arm64', [base.instructions.GROUP])  # type: TargetISA
 A64 = CPUMode('A64', ISA)
 
 # TODO: Refine these
diff --git a/lib/codegen/meta/isa/riscv/__init__.py b/lib/codegen/meta/isa/riscv/__init__.py
index f40086414d..b58dd68ae2 100644
--- a/lib/codegen/meta/isa/riscv/__init__.py
+++ b/lib/codegen/meta/isa/riscv/__init__.py
@@ -27,6 +27,7 @@ RV32G / RV64G
 from __future__ import absolute_import
 from . import defs
 from . import encodings, settings, registers  # noqa
+from cdsl.isa import TargetISA  # noqa
 
 # Re-export the primary target ISA definition.
-ISA = defs.ISA.finish()
+ISA = defs.ISA.finish()  # type: TargetISA
diff --git a/lib/codegen/meta/isa/riscv/defs.py b/lib/codegen/meta/isa/riscv/defs.py
index 485dbd7ef0..404895c502 100644
--- a/lib/codegen/meta/isa/riscv/defs.py
+++ b/lib/codegen/meta/isa/riscv/defs.py
@@ -7,7 +7,7 @@ from __future__ import absolute_import
 from cdsl.isa import TargetISA, CPUMode
 import base.instructions
 
-ISA = TargetISA('riscv', [base.instructions.GROUP])
+ISA = TargetISA('riscv', [base.instructions.GROUP])  # type: TargetISA
 
 # CPU modes for 32-bit and 64-bit operation.
 RV32 = CPUMode('RV32', ISA)
diff --git a/lib/codegen/meta/isa/x86/__init__.py b/lib/codegen/meta/isa/x86/__init__.py
index d87b95964a..93e71b316c 100644
--- a/lib/codegen/meta/isa/x86/__init__.py
+++ b/lib/codegen/meta/isa/x86/__init__.py
@@ -16,6 +16,7 @@ This target ISA generates code for x86 CPUs with two separate CPU modes:
 from __future__ import absolute_import
 from . import defs
 from . import encodings, settings, registers  # noqa
+from cdsl.isa import TargetISA  # noqa
 
 # Re-export the primary target ISA definition.
-ISA = defs.ISA.finish()
+ISA = defs.ISA.finish()  # type: TargetISA
diff --git a/lib/codegen/meta/isa/x86/defs.py b/lib/codegen/meta/isa/x86/defs.py
index 32c54ab620..00ac2bbbf1 100644
--- a/lib/codegen/meta/isa/x86/defs.py
+++ b/lib/codegen/meta/isa/x86/defs.py
@@ -9,7 +9,7 @@ import base.instructions
 from . import instructions as x86
 from base.immediates import floatcc
 
-ISA = TargetISA('x86', [base.instructions.GROUP, x86.GROUP])
+ISA = TargetISA('x86', [base.instructions.GROUP, x86.GROUP])  # type: TargetISA
 
 # CPU modes for 32-bit and 64-bit operation.
 X86_64 = CPUMode('I64', ISA)
diff --git a/lib/codegen/meta/mypy.ini b/lib/codegen/meta/mypy.ini
index 7046100b4c..877e4c9ff5 100644
--- a/lib/codegen/meta/mypy.ini
+++ b/lib/codegen/meta/mypy.ini
@@ -2,3 +2,4 @@
 disallow_untyped_defs = True
 warn_unused_ignores = True
 warn_return_any = True
+strict_optional = False