From 84471a8431db79aa41d4b8a900c7a635d43e0011 Mon Sep 17 00:00:00 2001
From: Jakob Stoklund Olesen <jolesen@mozilla.com>
Date: Wed, 27 Sep 2017 11:59:50 -0700
Subject: [PATCH] Add some very basic support for the Intel32 ABI.

In 32-bit mode, all function arguments are passed on the stack, not in
registers.

This ABI support is not complete or properly tested, but at least it
doesn't try to pass arguments in r8.
---
 cranelift/filetests/isa/intel/abi32.cton      | 20 +++++++++++++++++++
 .../filetests/isa/intel/legalize-custom.cton  |  8 ++++----
 .../filetests/regalloc/intel-regres.cton      |  6 ++++++
 lib/cretonne/src/isa/intel/abi.rs             | 12 +++++++++--
 4 files changed, 40 insertions(+), 6 deletions(-)
 create mode 100644 cranelift/filetests/isa/intel/abi32.cton

diff --git a/cranelift/filetests/isa/intel/abi32.cton b/cranelift/filetests/isa/intel/abi32.cton
new file mode 100644
index 0000000000..c7e399960c
--- /dev/null
+++ b/cranelift/filetests/isa/intel/abi32.cton
@@ -0,0 +1,20 @@
+; Test the legalization of function signatures.
+test legalizer
+isa intel
+
+; regex: V=v\d+
+
+function %f() {
+    sig0 = (i32) -> i32 native
+    ; check: sig0 = (i32 [0]) -> i32 [%rax] native
+
+    sig1 = (i64) -> b1 native
+    ; check: sig1 = (i32 [0], i32 [4]) -> b1 [%rax] native
+
+    sig2 = (f32, i64) -> f64 native
+    ; check: sig2 = (f32 [0], i32 [4], i32 [8]) -> f64 [%xmm0] native
+
+ebb0:
+    return
+}
+
diff --git a/cranelift/filetests/isa/intel/legalize-custom.cton b/cranelift/filetests/isa/intel/legalize-custom.cton
index 94aa7ab1d2..0327e0a317 100644
--- a/cranelift/filetests/isa/intel/legalize-custom.cton
+++ b/cranelift/filetests/isa/intel/legalize-custom.cton
@@ -11,7 +11,7 @@ function %cond_trap(i32) {
 ebb0(v1: i32):
     trapz v1, user67
     return
-    ; check: $ebb0($v1: i32):
+    ; check: $ebb0($v1: i32
     ; nextln: brnz $v1, $(new=$EBB)
     ; nextln: trap user67
     ; check: $new:
@@ -22,7 +22,7 @@ function %cond_trap2(i32) {
 ebb0(v1: i32):
     trapnz v1, int_ovf
     return
-    ; check: $ebb0($v1: i32):
+    ; check: $ebb0($v1: i32
     ; nextln: brz $v1, $(new=$EBB)
     ; nextln: trap int_ovf
     ; check: $new:
@@ -34,7 +34,7 @@ ebb0(v1: i32):
     v2 = icmp_imm eq v1, 6
     trapz v2, user7
     return
-    ; check: $ebb0($v1: i32):
+    ; check: $ebb0($v1: i32
     ; check: brnz $v2, $(new=$EBB)
     ; nextln: trap user7
     ; check: $new:
@@ -46,7 +46,7 @@ ebb0(v1: i32):
     v2 = icmp_imm eq v1, 6
     trapnz v2, user9
     return
-    ; check: $ebb0($v1: i32):
+    ; check: $ebb0($v1: i32
     ; check: brz $v2, $(new=$EBB)
     ; nextln: trap user9
     ; check: $new:
diff --git a/cranelift/filetests/regalloc/intel-regres.cton b/cranelift/filetests/regalloc/intel-regres.cton
index 24d13f5216..0de1b620c5 100644
--- a/cranelift/filetests/regalloc/intel-regres.cton
+++ b/cranelift/filetests/regalloc/intel-regres.cton
@@ -38,3 +38,9 @@ ebb2(v4: i32, v5: i32, v7: i32):
 ebb3:
     return v5
 }
+
+function %select_i64(i64, i64, i32) -> i64 {
+ebb0(v0: i64, v1: i64, v2: i32):
+    v3 = select v2, v0, v1
+    return v3
+}
diff --git a/lib/cretonne/src/isa/intel/abi.rs b/lib/cretonne/src/isa/intel/abi.rs
index 7a051905d4..c6bbe7fb2a 100644
--- a/lib/cretonne/src/isa/intel/abi.rs
+++ b/lib/cretonne/src/isa/intel/abi.rs
@@ -106,9 +106,17 @@ impl ArgAssigner for Args {
 
 /// Legalize `sig`.
 pub fn legalize_signature(sig: &mut ir::Signature, flags: &shared_settings::Flags, _current: bool) {
-    let bits = if flags.is_64bit() { 64 } else { 32 };
+    let bits;
+    let mut args;
+
+    if flags.is_64bit() {
+        bits = 64;
+        args = Args::new(bits, &ARG_GPRS, 8);
+    } else {
+        bits = 32;
+        args = Args::new(bits, &[], 0);
+    }
 
-    let mut args = Args::new(bits, &ARG_GPRS, 8);
     legalize_args(&mut sig.argument_types, &mut args);
 
     let mut rets = Args::new(bits, &RET_GPRS, 2);