Implement initial emission of constants
This approach suffers from memory-size bloat during compile time due to the desire to de-duplicate the constants emitted and reduce runtime memory-size. As a first step, though, this provides an end-to-end mechanism for constants to be emitted in the MachBuffer islands.
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@@ -3345,17 +3345,21 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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}
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Opcode::Vconst => {
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let val = if let &InstructionData::UnaryConst {
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let used_constant = if let &InstructionData::UnaryConst {
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constant_handle, ..
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} = ctx.data(insn)
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{
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ctx.get_constant_data(constant_handle).clone().into_vec()
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ctx.use_constant(VCodeConstantData::Pool(
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constant_handle,
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ctx.get_constant_data(constant_handle).clone(),
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))
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} else {
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unreachable!("vconst should always have unary_const format")
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};
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// TODO use Inst::gen_constant() instead.
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let dst = get_output_reg(ctx, outputs[0]);
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let ty = ty.unwrap();
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ctx.emit(Inst::xmm_load_const_seq(val, dst, ty));
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ctx.emit(Inst::xmm_load_const(used_constant, dst, ty));
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}
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Opcode::RawBitcast => {
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@@ -3396,8 +3400,9 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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.map(|&b| if b > 15 { b.wrapping_sub(16) } else { b })
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.map(zero_unknown_lane_index)
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.collect();
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let constant = ctx.use_constant(VCodeConstantData::Generated(constructed_mask));
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let tmp = ctx.alloc_tmp(RegClass::V128, types::I8X16);
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ctx.emit(Inst::xmm_load_const_seq(constructed_mask, tmp, ty));
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ctx.emit(Inst::xmm_load_const(constant, tmp, ty));
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// After loading the constructed mask in a temporary register, we use this to
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// shuffle the `dst` register (remember that, in this case, it is the same as
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// `src` so we disregard this register).
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@@ -3416,8 +3421,9 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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let tmp0 = ctx.alloc_tmp(RegClass::V128, lhs_ty);
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ctx.emit(Inst::gen_move(tmp0, lhs, lhs_ty));
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let constructed_mask = mask.iter().cloned().map(zero_unknown_lane_index).collect();
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let constant = ctx.use_constant(VCodeConstantData::Generated(constructed_mask));
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let tmp1 = ctx.alloc_tmp(RegClass::V128, types::I8X16);
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ctx.emit(Inst::xmm_load_const_seq(constructed_mask, tmp1, ty));
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ctx.emit(Inst::xmm_load_const(constant, tmp1, ty));
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ctx.emit(Inst::xmm_rm_r(
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SseOpcode::Pshufb,
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RegMem::from(tmp1),
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@@ -3431,8 +3437,9 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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.map(|b| b.wrapping_sub(16))
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.map(zero_unknown_lane_index)
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.collect();
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let constant = ctx.use_constant(VCodeConstantData::Generated(constructed_mask));
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let tmp2 = ctx.alloc_tmp(RegClass::V128, types::I8X16);
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ctx.emit(Inst::xmm_load_const_seq(constructed_mask, tmp2, ty));
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ctx.emit(Inst::xmm_load_const(constant, tmp2, ty));
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ctx.emit(Inst::xmm_rm_r(
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SseOpcode::Pshufb,
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RegMem::from(tmp2),
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@@ -3469,11 +3476,12 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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// Create a mask for zeroing out-of-bounds lanes of the swizzle mask.
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let zero_mask = ctx.alloc_tmp(RegClass::V128, types::I8X16);
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let zero_mask_value = vec![
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static ZERO_MASK_VALUE: [u8; 16] = [
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0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70,
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0x70, 0x70,
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];
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ctx.emit(Inst::xmm_load_const_seq(zero_mask_value, zero_mask, ty));
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let constant = ctx.use_constant(VCodeConstantData::WellKnown(&ZERO_MASK_VALUE));
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ctx.emit(Inst::xmm_load_const(constant, zero_mask, ty));
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// Use the `zero_mask` on a writable `swizzle_mask`.
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let swizzle_mask = Writable::from_reg(swizzle_mask);
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