Mass rename Ebb and relatives to Block (#1365)

* Manually rename BasicBlock to BlockPredecessor

BasicBlock is a pair of (Ebb, Inst) that is used to represent the
basic block subcomponent of an Ebb that is a predecessor to an Ebb.

Eventually we will be able to remove this struct, but for now it
makes sense to give it a non-conflicting name so that we can start
to transition Ebb to represent a basic block.

I have not updated any comments that refer to BasicBlock, as
eventually we will remove BlockPredecessor and replace with Block,
which is a basic block, so the comments will become correct.

* Manually rename SSABuilder block types to avoid conflict

SSABuilder has its own Block and BlockData types. These along with
associated identifier will cause conflicts in a later commit, so
they are renamed to be more verbose here.

* Automatically rename 'Ebb' to 'Block' in *.rs

* Automatically rename 'EBB' to 'block' in *.rs

* Automatically rename 'ebb' to 'block' in *.rs

* Automatically rename 'extended basic block' to 'basic block' in *.rs

* Automatically rename 'an basic block' to 'a basic block' in *.rs

* Manually update comment for `Block`

`Block`'s wikipedia article required an update.

* Automatically rename 'an `Block`' to 'a `Block`' in *.rs

* Automatically rename 'extended_basic_block' to 'basic_block' in *.rs

* Automatically rename 'ebb' to 'block' in *.clif

* Manually rename clif constant that contains 'ebb' as substring to avoid conflict

* Automatically rename filecheck uses of 'EBB' to 'BB'

'regex: EBB' -> 'regex: BB'
'$EBB' -> '$BB'

* Automatically rename 'EBB' 'Ebb' to 'block' in *.clif

* Automatically rename 'an block' to 'a block' in *.clif

* Fix broken testcase when function name length increases

Test function names are limited to 16 characters. This causes
the new longer name to be truncated and fail a filecheck test. An
outdated comment was also fixed.
This commit is contained in:
Ryan Hunt
2020-02-07 10:46:47 -06:00
committed by GitHub
parent a136d1cb00
commit 832666c45e
370 changed files with 8090 additions and 7988 deletions

View File

@@ -3,39 +3,39 @@ target riscv32
function %simple_loop(i32) -> i32 {
ebb0(v0: i32):
jump ebb1(v0)
block0(v0: i32):
jump block1(v0)
ebb1(v1: i32):
block1(v1: i32):
v2 = iconst.i32 1
v3 = iconst.i32 2
v4 = iadd v2, v3
brz v1, ebb3(v1)
jump ebb2
brz v1, block3(v1)
jump block2
ebb2:
block2:
v5 = isub v1, v2
jump ebb1(v5)
jump block1(v5)
ebb3(v6: i32):
block3(v6: i32):
return v6
}
; sameln: function %simple_loop
; nextln: ebb0(v0: i32):
; nextln: block0(v0: i32):
; nextln: v2 = iconst.i32 1
; nextln: v3 = iconst.i32 2
; nextln: v4 = iadd v2, v3
; nextln: jump ebb1(v0)
; nextln: jump block1(v0)
; nextln:
; nextln: ebb1(v1: i32):
; nextln: brz v1, ebb3(v1)
; nextln: jump ebb2
; nextln: block1(v1: i32):
; nextln: brz v1, block3(v1)
; nextln: jump block2
; nextln:
; nextln: ebb2:
; nextln: block2:
; nextln: v5 = isub.i32 v1, v2
; nextln: jump ebb1(v5)
; nextln: jump block1(v5)
; nextln:
; nextln: ebb3(v6: i32):
; nextln: block3(v6: i32):
; nextln: return v6
; nextln: }

View File

@@ -2,95 +2,95 @@ test licm
target riscv32
function %complex(i32) -> i32 system_v {
ebb0(v0: i32):
[UJ#1b] jump ebb1(v0)
block0(v0: i32):
[UJ#1b] jump block1(v0)
ebb1(v1: i32):
block1(v1: i32):
v2 = iconst.i32 1
v3 = iconst.i32 4
v4 = iadd v2, v1
[SBzero#18] brz v1, ebb2(v2)
[UJ#1b] jump ebb4(v4)
[SBzero#18] brz v1, block2(v2)
[UJ#1b] jump block4(v4)
ebb2(v5: i32):
block2(v5: i32):
v6 = iconst.i32 2
v7 = iadd v5, v4
v8 = iadd v6, v1
[UJ#1b] jump ebb3(v8)
[UJ#1b] jump block3(v8)
ebb3(v9: i32):
block3(v9: i32):
v10 = iadd v9, v5
v11 = iadd.i32 v1, v4
[SBzero#18] brz.i32 v1, ebb2(v9)
[UJ#1b] jump ebb6(v10)
[SBzero#18] brz.i32 v1, block2(v9)
[UJ#1b] jump block6(v10)
ebb4(v12: i32):
block4(v12: i32):
v13 = iconst.i32 3
v14 = iadd v12, v13
v15 = iadd.i32 v4, v13
[UJ#1b] jump ebb5(v13)
[UJ#1b] jump block5(v13)
ebb5(v16: i32):
block5(v16: i32):
v17 = iadd.i32 v14, v4
[SBzero#18] brz.i32 v1, ebb4(v16)
[UJ#1b] jump ebb6(v16)
[SBzero#18] brz.i32 v1, block4(v16)
[UJ#1b] jump block6(v16)
ebb6(v18: i32):
block6(v18: i32):
v19 = iadd v18, v2
v20 = iadd.i32 v2, v3
[SBzero#18] brz.i32 v1, ebb1(v20)
[UJ#1b] jump ebb7
[SBzero#18] brz.i32 v1, block1(v20)
[UJ#1b] jump block7
ebb7:
block7:
[Iret#19] return v19
}
; sameln: function %complex
; nextln: ebb0(v0: i32):
; nextln: block0(v0: i32):
; nextln: v2 = iconst.i32 1
; nextln: v3 = iconst.i32 4
; nextln: v6 = iconst.i32 2
; nextln: v13 = iconst.i32 3
; nextln: v20 = iadd v2, v3
; nextln: jump ebb1(v0)
; nextln: jump block1(v0)
; nextln:
; nextln: ebb1(v1: i32):
; nextln: block1(v1: i32):
; nextln: v4 = iadd.i32 v2, v1
; nextln: brz v1, ebb8(v2)
; nextln: jump ebb9(v4)
; nextln: brz v1, block8(v2)
; nextln: jump block9(v4)
; nextln:
; nextln: ebb8(v21: i32):
; nextln: block8(v21: i32):
; nextln: v8 = iadd.i32 v6, v1
; nextln: v11 = iadd.i32 v1, v4
; nextln: jump ebb2(v21)
; nextln: jump block2(v21)
; nextln:
; nextln: ebb2(v5: i32):
; nextln: block2(v5: i32):
; nextln: v7 = iadd v5, v4
; nextln: jump ebb3(v8)
; nextln: jump block3(v8)
; nextln:
; nextln: ebb3(v9: i32):
; nextln: block3(v9: i32):
; nextln: v10 = iadd v9, v5
; nextln: brz.i32 v1, ebb2(v9)
; nextln: jump ebb6(v10)
; nextln: brz.i32 v1, block2(v9)
; nextln: jump block6(v10)
; nextln:
; nextln: ebb9(v22: i32):
; nextln: block9(v22: i32):
; nextln: v15 = iadd.i32 v4, v13
; nextln: jump ebb4(v22)
; nextln: jump block4(v22)
; nextln:
; nextln: ebb4(v12: i32):
; nextln: block4(v12: i32):
; nextln: v14 = iadd v12, v13
; nextln: jump ebb5(v13)
; nextln: jump block5(v13)
; nextln:
; nextln: ebb5(v16: i32):
; nextln: block5(v16: i32):
; nextln: v17 = iadd.i32 v14, v4
; nextln: brz.i32 v1, ebb4(v16)
; nextln: jump ebb6(v16)
; nextln: brz.i32 v1, block4(v16)
; nextln: jump block6(v16)
; nextln:
; nextln: ebb6(v18: i32):
; nextln: block6(v18: i32):
; nextln: v19 = iadd v18, v2
; nextln: brz.i32 v1, ebb1(v20)
; nextln: jump ebb7
; nextln: brz.i32 v1, block1(v20)
; nextln: jump block7
; nextln:
; nextln: ebb7:
; nextln: block7:
; nextln: return v19
; nextln: }

View File

@@ -5,50 +5,50 @@ target riscv32
function %critical_edge(i32, i32) -> i32 {
ebb0(v0: i32, v7: i32):
[SBzero#38] brnz v7, ebb2(v0)
[UJ#1b] jump ebb1
block0(v0: i32, v7: i32):
[SBzero#38] brnz v7, block2(v0)
[UJ#1b] jump block1
ebb1:
block1:
[Iret#19] return v0
ebb2(v1: i32):
block2(v1: i32):
v2 = iconst.i32 1
v3 = iconst.i32 2
v4 = iadd v2, v3
[SBzero#18] brz v1, ebb4(v1)
[UJ#1b] jump ebb3
[SBzero#18] brz v1, block4(v1)
[UJ#1b] jump block3
ebb3:
block3:
v5 = isub v1, v2
[UJ#1b] jump ebb2(v5)
[UJ#1b] jump block2(v5)
ebb4(v6: i32):
block4(v6: i32):
[Iret#19] return v6
}
; sameln: function %critical_edge
; nextln: ebb0(v0: i32, v7: i32):
; nextln: brnz v7, ebb5(v0)
; nextln: jump ebb1
; nextln: block0(v0: i32, v7: i32):
; nextln: brnz v7, block5(v0)
; nextln: jump block1
; nextln:
; nextln: ebb1:
; nextln: block1:
; nextln: return v0
; nextln:
; nextln: ebb5(v8: i32):
; nextln: block5(v8: i32):
; nextln: v2 = iconst.i32 1
; nextln: v3 = iconst.i32 2
; nextln: v4 = iadd v2, v3
; nextln: jump ebb2(v8)
; nextln: jump block2(v8)
; nextln:
; nextln: ebb2(v1: i32):
; nextln: brz v1, ebb4(v1)
; nextln: jump ebb3
; nextln: block2(v1: i32):
; nextln: brz v1, block4(v1)
; nextln: jump block3
; nextln:
; nextln: ebb3:
; nextln: block3:
; nextln: v5 = isub.i32 v1, v2
; nextln: jump ebb2(v5)
; nextln: jump block2(v5)
; nextln:
; nextln: ebb4(v6: i32):
; nextln: block4(v6: i32):
; nextln: return v6
; nextln: }

View File

@@ -4,39 +4,39 @@ target riscv32
; Ensure that instructions emitted by LICM get encodings.
function %simple_loop(i32) -> i32 {
ebb0(v0: i32):
[UJ#1b] jump ebb1(v0)
block0(v0: i32):
[UJ#1b] jump block1(v0)
ebb1(v1: i32):
block1(v1: i32):
[Iz#04,%x0] v2 = iconst.i32 1
[Iz#04,%x1] v3 = iconst.i32 2
[R#0c,%x2] v4 = iadd v2, v3
[SBzero#18] brz v1, ebb3(v1)
[UJ#1b] jump ebb2
[SBzero#18] brz v1, block3(v1)
[UJ#1b] jump block2
ebb2:
block2:
[R#200c,%x5] v5 = isub v1, v2
[UJ#1b] jump ebb1(v5)
[UJ#1b] jump block1(v5)
ebb3(v6: i32):
block3(v6: i32):
[Iret#19] return v6
}
; check: function
; nextln: ebb0(v0: i32):
; nextln: block0(v0: i32):
; nextln: [Iz#04,%x0] v2 = iconst.i32 1
; nextln: [Iz#04,%x1] v3 = iconst.i32 2
; nextln: [R#0c,%x2] v4 = iadd v2, v3
; nextln: [UJ#1b] jump ebb1(v0)
; nextln: [UJ#1b] jump block1(v0)
; nextln:
; nextln: ebb1(v1: i32):
; nextln: [SBzero#18] brz v1, ebb3(v1)
; nextln: [UJ#1b] jump ebb2
; nextln: block1(v1: i32):
; nextln: [SBzero#18] brz v1, block3(v1)
; nextln: [UJ#1b] jump block2
; nextln:
; nextln: ebb2:
; nextln: block2:
; nextln: [R#200c,%x5] v5 = isub.i32 v1, v2
; nextln: [UJ#1b] jump ebb1(v5)
; nextln: [UJ#1b] jump block1(v5)
; nextln:
; nextln: ebb3(v6: i32):
; nextln: block3(v6: i32):
; nextln: [Iret#19] return v6
; nextln: }

View File

@@ -2,32 +2,32 @@ test licm
target x86_64
function %dont_hoist_jump_table_entry_during_licm() {
jt0 = jump_table [ebb1, ebb1]
jt0 = jump_table [block1, block1]
ebb0:
fallthrough ebb1
block0:
fallthrough block1
ebb1: ; the loop!
block1: ; the loop!
v2 = iconst.i32 42
v3 = ifcmp_imm v2, 0
brif uge v3, ebb1
fallthrough ebb2
brif uge v3, block1
fallthrough block2
ebb2:
block2:
v1 = iconst.i64 -14
v8 = ifcmp_imm v1, 2
brif uge v8, ebb1
jump ebb3
brif uge v8, block1
jump block3
ebb3:
block3:
v5 = jump_table_base.i64 jt0
v6 = jump_table_entry.i64 v1, v5, 4, jt0
v7 = iadd v5, v6
indirect_jump_table_br v7, jt0
; check: ebb2:
; check: block2:
; nextln: v8 = ifcmp_imm.i64 v1, 2
; nextln: brif uge v8, ebb1
; nextln: jump ebb3
; check: ebb3:
; nextln: brif uge v8, block1
; nextln: jump block3
; check: block3:
; nextln: jump_table_entry.i64
}

View File

@@ -10,22 +10,22 @@ function %hoist_load(i32, i64 vmctx) -> i32 {
gv1 = load.i64 notrap aligned readonly gv0
heap0 = static gv1, min 0x1_0000, bound 0x1_0000_0000, offset_guard 0x8000_0000, index_type i32
ebb0(v0: i32, v1: i64):
jump ebb1(v0, v1)
block0(v0: i32, v1: i64):
jump block1(v0, v1)
ebb1(v2: i32, v3: i64):
block1(v2: i32, v3: i64):
v4 = iconst.i32 1
v5 = heap_addr.i64 heap0, v4, 1
v6 = load.i32 notrap aligned readonly v5
v7 = iadd v2, v6
brz v2, ebb3(v2)
jump ebb2
brz v2, block3(v2)
jump block2
ebb2:
block2:
v8 = isub v2, v4
jump ebb1(v8, v3)
jump block1(v8, v3)
ebb3(v9: i32):
block3(v9: i32):
return v9
}
@@ -34,21 +34,21 @@ ebb3(v9: i32):
; nextln: gv1 = load.i64 notrap aligned readonly gv0
; nextln: heap0 = static gv1, min 0x0001_0000, bound 0x0001_0000_0000, offset_guard 0x8000_0000, index_type i32
; nextln:
; nextln: ebb0(v0: i32, v1: i64):
; nextln: block0(v0: i32, v1: i64):
; nextln: v4 = iconst.i32 1
; nextln: v5 = heap_addr.i64 heap0, v4, 1
; nextln: v6 = load.i32 notrap aligned readonly v5
; nextln: jump ebb1(v0, v1)
; nextln: jump block1(v0, v1)
; nextln:
; nextln: ebb1(v2: i32, v3: i64):
; nextln: block1(v2: i32, v3: i64):
; nextln: v7 = iadd v2, v6
; nextln: brz v2, ebb3(v2)
; nextln: jump ebb2
; nextln: brz v2, block3(v2)
; nextln: jump block2
; nextln:
; nextln: ebb2:
; nextln: block2:
; nextln: v8 = isub.i32 v2, v4
; nextln: jump ebb1(v8, v3)
; nextln: jump block1(v8, v3)
; nextln:
; nextln: ebb3(v9: i32):
; nextln: block3(v9: i32):
; nextln: return v9
; nextln: }

View File

@@ -3,57 +3,57 @@ target riscv32
function %multiple_blocks(i32) -> i32 {
ebb0(v0: i32):
jump ebb1(v0)
block0(v0: i32):
jump block1(v0)
ebb1(v10: i32):
block1(v10: i32):
v11 = iconst.i32 1
v12 = iconst.i32 2
v13 = iadd v11, v12
brz v10, ebb4(v10)
jump ebb2
brz v10, block4(v10)
jump block2
ebb2:
block2:
v15 = isub v10, v11
brz v15, ebb5(v15)
jump ebb3
brz v15, block5(v15)
jump block3
ebb3:
block3:
v14 = isub v10, v11
jump ebb1(v14)
jump block1(v14)
ebb4(v20: i32):
block4(v20: i32):
return v20
ebb5(v30: i32):
block5(v30: i32):
v31 = iadd v11, v13
jump ebb1(v30)
jump block1(v30)
}
; sameln:function %multiple_blocks(i32) -> i32 {
; nextln: ebb0(v0: i32):
; nextln: block0(v0: i32):
; nextln: v11 = iconst.i32 1
; nextln: v12 = iconst.i32 2
; nextln: v13 = iadd v11, v12
; nextln: v31 = iadd v11, v13
; nextln: jump ebb1(v0)
; nextln: jump block1(v0)
; nextln:
; nextln: ebb1(v10: i32):
; nextln: brz v10, ebb4(v10)
; nextln: jump ebb2
; nextln: block1(v10: i32):
; nextln: brz v10, block4(v10)
; nextln: jump block2
; nextln:
; nextln: ebb2:
; nextln: block2:
; nextln: v15 = isub.i32 v10, v11
; nextln: brz v15, ebb5(v15)
; nextln: jump ebb3
; nextln: brz v15, block5(v15)
; nextln: jump block3
; nextln:
; nextln: ebb3:
; nextln: block3:
; nextln: v14 = isub.i32 v10, v11
; nextln: jump ebb1(v14)
; nextln: jump block1(v14)
; nextln:
; nextln: ebb4(v20: i32):
; nextln: block4(v20: i32):
; nextln: return v20
; nextln:
; nextln: ebb5(v30: i32):
; nextln: jump ebb1(v30)
; nextln: block5(v30: i32):
; nextln: jump block1(v30)
; nextln: }

View File

@@ -3,60 +3,60 @@ target riscv32
function %nested_loops(i32) -> i32 {
ebb0(v0: i32):
jump ebb1(v0)
block0(v0: i32):
jump block1(v0)
ebb1(v1: i32):
block1(v1: i32):
v2 = iconst.i32 1
v3 = iconst.i32 2
v4 = iadd v2, v3
v5 = isub v1, v2
jump ebb2(v5, v5)
jump block2(v5, v5)
ebb2(v10: i32, v11: i32):
brz v11, ebb4(v10)
jump ebb3
block2(v10: i32, v11: i32):
brz v11, block4(v10)
jump block3
ebb3:
block3:
v12 = iconst.i32 1
v15 = iadd v12, v5
v13 = isub v11, v12
jump ebb2(v10,v13)
jump block2(v10,v13)
ebb4(v20: i32):
brz v20, ebb5(v20)
jump ebb1(v20)
block4(v20: i32):
brz v20, block5(v20)
jump block1(v20)
ebb5(v30: i32):
block5(v30: i32):
return v30
}
; sameln:function %nested_loops(i32) -> i32 {
; nextln: ebb0(v0: i32):
; nextln: block0(v0: i32):
; nextln: v2 = iconst.i32 1
; nextln: v3 = iconst.i32 2
; nextln: v4 = iadd v2, v3
; nextln: v12 = iconst.i32 1
; nextln: jump ebb1(v0)
; nextln: jump block1(v0)
; nextln:
; nextln: ebb1(v1: i32):
; nextln: block1(v1: i32):
; nextln: v5 = isub v1, v2
; nextln: v15 = iadd.i32 v12, v5
; nextln: jump ebb2(v5, v5)
; nextln: jump block2(v5, v5)
; nextln:
; nextln: ebb2(v10: i32, v11: i32):
; nextln: brz v11, ebb4(v10)
; nextln: jump ebb3
; nextln: block2(v10: i32, v11: i32):
; nextln: brz v11, block4(v10)
; nextln: jump block3
; nextln:
; nextln: ebb3:
; nextln: block3:
; nextln: v13 = isub.i32 v11, v12
; nextln: jump ebb2(v10, v13)
; nextln: jump block2(v10, v13)
; nextln:
; nextln: ebb4(v20: i32):
; nextln: brz v20, ebb5(v20)
; nextln: jump ebb1(v20)
; nextln: block4(v20: i32):
; nextln: brz v20, block5(v20)
; nextln: jump block1(v20)
; nextln:
; nextln: ebb5(v30: i32):
; nextln: block5(v30: i32):
; nextln: return v30
; nextln: }

View File

@@ -3,92 +3,92 @@ target riscv32
function %other_side_effects(i32) -> i32 {
ebb0(v0: i32):
jump ebb1(v0)
block0(v0: i32):
jump block1(v0)
ebb1(v1: i32):
block1(v1: i32):
regmove.i32 v0, %x10 -> %x20
; check: ebb1(v1: i32):
; check: block1(v1: i32):
; check: regmove.i32 v0, %x10 -> %x20
v2 = iconst.i32 1
brz v1, ebb3(v1)
jump ebb2
brz v1, block3(v1)
jump block2
ebb2:
block2:
v5 = isub v1, v2
jump ebb1(v5)
jump block1(v5)
ebb3(v6: i32):
block3(v6: i32):
return v6
}
function %cpu_flags(i32, i32) -> i32 {
ebb0(v0: i32, v1: i32):
jump ebb1(v0, v1)
block0(v0: i32, v1: i32):
jump block1(v0, v1)
ebb1(v2: i32, v3: i32):
block1(v2: i32, v3: i32):
v4 = ifcmp.i32 v0, v1
v5 = selectif.i32 eq v4, v2, v3
; check: ebb1(v2: i32, v3: i32):
; check: block1(v2: i32, v3: i32):
; check: ifcmp.i32 v0, v1
; check: v5 = selectif.i32 eq v4, v2, v3
v8 = iconst.i32 1
brz v1, ebb3(v1)
jump ebb2
brz v1, block3(v1)
jump block2
ebb2:
block2:
v9 = isub v1, v8
v10 = iadd v1, v8
jump ebb1(v9, v10)
jump block1(v9, v10)
ebb3(v6: i32):
block3(v6: i32):
return v6
}
function %spill(i32, i32) -> i32 {
ebb0(v0: i32, v1: i32):
block0(v0: i32, v1: i32):
v2 = spill.i32 v0
jump ebb1(v0, v1)
jump block1(v0, v1)
ebb1(v3: i32, v4: i32):
block1(v3: i32, v4: i32):
v5 = spill.i32 v1
v6 = fill.i32 v2
v7 = fill.i32 v5
; check: ebb1(v3: i32, v4: i32):
; check: block1(v3: i32, v4: i32):
; check: v5 = spill.i32 v1
; check: v6 = fill.i32 v2
; check: v7 = fill v5
brz v1, ebb3(v1)
jump ebb2
brz v1, block3(v1)
jump block2
ebb2:
block2:
v9 = isub v1, v4
jump ebb1(v9, v3)
jump block1(v9, v3)
ebb3(v10: i32):
block3(v10: i32):
return v10
}
function %non_invariant_aliases(i32) -> i32 {
ebb0(v0: i32):
jump ebb1(v0)
block0(v0: i32):
jump block1(v0)
ebb1(v1: i32):
block1(v1: i32):
v8 -> v1
v9 -> v1
v2 = iadd v8, v9
; check: ebb1(v1: i32):
; check: block1(v1: i32):
; check: v2 = iadd v8, v9
brz v1, ebb3(v1)
jump ebb2
brz v1, block3(v1)
jump block2
ebb2:
block2:
v5 = isub v1, v2
jump ebb1(v5)
jump block1(v5)
ebb3(v6: i32):
block3(v6: i32):
return v6
}

View File

@@ -11,22 +11,22 @@ function %hoist_load(i32, i64 vmctx) -> i32 {
gv1 = load.i64 notrap aligned readonly gv0
heap0 = static gv1, min 0x1_0000, bound 0x1_0000_0000, offset_guard 0x8000_0000, index_type i32
ebb0(v0: i32, v1: i64):
block0(v0: i32, v1: i64):
v4 = iconst.i32 1
v5 = heap_addr.i64 heap0, v4, 1
jump ebb1(v0, v1)
jump block1(v0, v1)
ebb1(v2: i32, v3: i64):
block1(v2: i32, v3: i64):
v6 = load.i32 notrap aligned v5
v7 = iadd v2, v6
brz v2, ebb3(v2)
jump ebb2
brz v2, block3(v2)
jump block2
ebb2:
block2:
v8 = isub v2, v4
jump ebb1(v8, v3)
jump block1(v8, v3)
ebb3(v9: i32):
block3(v9: i32):
return v9
}
@@ -35,21 +35,21 @@ ebb3(v9: i32):
; nextln: gv1 = load.i64 notrap aligned readonly gv0
; nextln: heap0 = static gv1, min 0x0001_0000, bound 0x0001_0000_0000, offset_guard 0x8000_0000, index_type i32
; nextln:
; nextln: ebb0(v0: i32, v1: i64):
; nextln: block0(v0: i32, v1: i64):
; nextln: v4 = iconst.i32 1
; nextln: v5 = heap_addr.i64 heap0, v4, 1
; nextln: jump ebb1(v0, v1)
; nextln: jump block1(v0, v1)
; nextln:
; nextln: ebb1(v2: i32, v3: i64):
; nextln: block1(v2: i32, v3: i64):
; nextln: v6 = load.i32 notrap aligned v5
; nextln: v7 = iadd v2, v6
; nextln: brz v2, ebb3(v2)
; nextln: jump ebb2
; nextln: brz v2, block3(v2)
; nextln: jump block2
; nextln:
; nextln: ebb2:
; nextln: block2:
; nextln: v8 = isub.i32 v2, v4
; nextln: jump ebb1(v8, v3)
; nextln: jump block1(v8, v3)
; nextln:
; nextln: ebb3(v9: i32):
; nextln: block3(v9: i32):
; nextln: return v9
; nextln: }

View File

@@ -11,22 +11,22 @@ function %hoist_load(i32, i64 vmctx) -> i32 {
gv1 = load.i64 notrap aligned readonly gv0
heap0 = static gv1, min 0x1_0000, bound 0x1_0000_0000, offset_guard 0x8000_0000, index_type i32
ebb0(v0: i32, v1: i64):
jump ebb1(v0, v1)
block0(v0: i32, v1: i64):
jump block1(v0, v1)
ebb1(v2: i32, v3: i64):
block1(v2: i32, v3: i64):
v4 = iconst.i32 1
v5 = heap_addr.i64 heap0, v4, 1
v6 = load.i32 aligned readonly v5
v7 = iadd v2, v6
brz v2, ebb3(v2)
jump ebb2
brz v2, block3(v2)
jump block2
ebb2:
block2:
v8 = isub v2, v4
jump ebb1(v8, v3)
jump block1(v8, v3)
ebb3(v9: i32):
block3(v9: i32):
return v9
}
@@ -35,21 +35,21 @@ ebb3(v9: i32):
; nextln: gv1 = load.i64 notrap aligned readonly gv0
; nextln: heap0 = static gv1, min 0x0001_0000, bound 0x0001_0000_0000, offset_guard 0x8000_0000, index_type i32
; nextln:
; nextln: ebb0(v0: i32, v1: i64):
; nextln: block0(v0: i32, v1: i64):
; nextln: v4 = iconst.i32 1
; nextln: v5 = heap_addr.i64 heap0, v4, 1
; nextln: jump ebb1(v0, v1)
; nextln: jump block1(v0, v1)
; nextln:
; nextln: ebb1(v2: i32, v3: i64):
; nextln: block1(v2: i32, v3: i64):
; nextln: v6 = load.i32 aligned readonly v5
; nextln: v7 = iadd v2, v6
; nextln: brz v2, ebb3(v2)
; nextln: jump ebb2
; nextln: brz v2, block3(v2)
; nextln: jump block2
; nextln:
; nextln: ebb2:
; nextln: block2:
; nextln: v8 = isub.i32 v2, v4
; nextln: jump ebb1(v8, v3)
; nextln: jump block1(v8, v3)
; nextln:
; nextln: ebb3(v9: i32):
; nextln: block3(v9: i32):
; nextln: return v9
; nextln: }