Remove the return_reg instruction.

RISC architectures that take a return address in a register can use a
special-purpose `link` return value to do so.

lib/cretonne/meta/base/instructions.py

@@ -155,25 +155,6 @@ x_return = Instruction(
         """,
         ins=rvals, is_return=True, is_terminator=True)
 
-raddr = Operand('raddr', iAddr, doc='Return address')
-
-return_reg = Instruction(
-        'return_reg', r"""
-        Return from the function to a return address held in a register.
-
-        Unconditionally transfer control to the calling function, passing the
-        provided return values. The list of return values must match the
-        function signature's return types.
-
-        This instruction should only be used by ISA-specific epilogue lowering
-        code. It is equivalent to :inst:`return`, but the return address is
-        provided explicitly in a register. This style of return instruction is
-        used by RISC architectures such as ARM and RISC-V. A normal
-        :inst:`return` will be legalized into this instruction on these
-        architectures.
-        """,
-        ins=(raddr, rvals), is_return=True, is_terminator=True)
-
 FN = Operand(
         'FN',
         entities.func_ref,

lib/cretonne/meta/isa/riscv/encodings.py

@@ -109,9 +109,8 @@ for inst,           f3 in [
     RV32.enc(inst.b1, SBzero, BRANCH(f3))
     RV64.enc(inst.b1, SBzero, BRANCH(f3))
 
-# Returns are a special case of JALR.
-# Note: Return stack predictors will only recognize this as a return when the
-# return address is provided in `x1`. We may want a special encoding to enforce
-# that.
-RV32.enc(base.return_reg.i32, Iret, JALR())
-RV64.enc(base.return_reg.i64, Iret, JALR())
+# Returns are a special case of JALR using %x1 to hold the return address.
+# The return address is provided by a special-purpose `link` return value that
+# is added by legalize_signature().
+RV32.enc(base.x_return, Iret, JALR())
+RV64.enc(base.x_return, Iret, JALR())