Remove printlns, make pushing stack arguments work properly

This commit is contained in:
Jef
2019-02-19 15:44:04 +01:00
parent f1d9ccb9e8
commit 830644e7d0
2 changed files with 18 additions and 10 deletions

View File

@@ -1372,20 +1372,32 @@ impl<M: ModuleContext> Context<'_, M> {
store!(i64_store, Rq, QWORD, "i64.store"); store!(i64_store, Rq, QWORD, "i64.store");
fn push_physical(&mut self, value: ValueLocation) -> ValueLocation { fn push_physical(&mut self, value: ValueLocation) -> ValueLocation {
self.block_state.depth.reserve(1);
match value { match value {
ValueLocation::Reg(gpr) => { ValueLocation::Reg(gpr) => {
self.block_state.depth.reserve(1);
// TODO: Proper stack allocation scheme // TODO: Proper stack allocation scheme
dynasm!(self.asm dynasm!(self.asm
; push Rq(gpr) ; push Rq(gpr)
); );
self.block_state.regs.release_scratch_gpr(gpr); self.block_state.regs.release_scratch_gpr(gpr);
}
ValueLocation::Stack(o) => {
let offset = self.adjusted_offset(o);
dynasm!(self.asm
; push QWORD [rsp + offset]
);
}
ValueLocation::Immediate(imm) => {
let gpr = self.block_state.regs.take_scratch_gpr();
dynasm!(self.asm
; mov Rq(gpr), QWORD imm
; push Rq(gpr)
);
self.block_state.regs.release_scratch_gpr(gpr);
}
}
ValueLocation::Stack(-(self.block_state.depth.0 as i32)) ValueLocation::Stack(-(self.block_state.depth.0 as i32))
} }
value => value,
}
}
fn push(&mut self, value: ValueLocation) { fn push(&mut self, value: ValueLocation) {
self.block_state.stack.push(value); self.block_state.stack.push(value);
@@ -1823,13 +1835,11 @@ impl<M: ModuleContext> Context<'_, M> {
for &loc in out_locs.iter().rev() { for &loc in out_locs.iter().rev() {
let val = self.pop(); let val = self.pop();
println!("{:?}", loc);
match loc { match loc {
CCLoc::Stack(offset) => { CCLoc::Stack(offset) => {
let offset = self.adjusted_offset(offset as i32 - depth as i32); let offset = self.adjusted_offset(offset as i32 - depth as i32);
if offset == -1 { if offset == -(WORD_SIZE as i32) {
self.push_physical(val); self.push_physical(val);
} else { } else {
let gpr = self.into_reg(val); let gpr = self.into_reg(val);
@@ -1856,8 +1866,6 @@ impl<M: ModuleContext> Context<'_, M> {
while !pending.is_empty() { while !pending.is_empty() {
try_count -= 1; try_count -= 1;
println!("{:?}", self.block_state);
if try_count == 0 { if try_count == 0 {
unimplemented!("We can't handle cycles in the register allocation right now"); unimplemented!("We can't handle cycles in the register allocation right now");
} }

View File

@@ -129,7 +129,7 @@ pub fn code(
&body, &body,
); );
if true { if false {
let mut microwasm = vec![]; let mut microwasm = vec![];
let mut microwasm_conv = MicrowasmConv::new( let mut microwasm_conv = MicrowasmConv::new(