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riscv64: Use a temporary when translating shift amount (#5375)

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Use a temporary when translating the shift amount, instead of reusing the destination register.
This commit is contained in:
Trevor Elliott
2022-12-05 12:54:14 -08:00
committed by GitHub
parent b475b9bd19
commit 817c2b205c
3 changed files with 154 additions and 155 deletions
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8
cranelift/codegen/src/isa/riscv64/lower/isle.rs
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@@ -293,15 +293,13 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Flags, IsaFlags, 6>
tmp.to_reg()
};
let len_sub_shamt = {
let tmp = self.temp_writable_reg(I64);
self.emit(&MInst::load_imm12(tmp, Imm12::from_bits(ty.bits() as i16)));
let len_sub_shamt = self.temp_writable_reg(I64);
self.emit(&MInst::load_imm12(
len_sub_shamt,
Imm12::from_bits(ty.bits() as i16),
));
self.emit(&MInst::AluRRR {
alu_op: AluOPRRR::Sub,
rd: len_sub_shamt,
rs1: len_sub_shamt.to_reg(),
rs1: tmp.to_reg(),
rs2: shamt,
});
len_sub_shamt.to_reg()