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x64: port some atomics to ISLE (#4212)

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* x64: port `fence` to ISLE
* x64: port `atomic_load` to ISLE
* x64: port `atomic_store` to ISLE
This commit is contained in:
Andrew Brown
2022-06-02 14:13:10 -07:00
committed by GitHub
parent 44d1dee76e
commit 816aae6aca
7 changed files with 58 additions and 43 deletions
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37
cranelift/codegen/src/isa/x64/lower.rs
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@@ -2234,46 +2234,15 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
}
Opcode::AtomicLoad => {
// This is a normal load. The x86-TSO memory model provides sufficient sequencing
// to satisfy the CLIF synchronisation requirements for `AtomicLoad` without the
// need for any fence instructions.
let data = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
let addr = lower_to_amode(ctx, inputs[0], 0);
let ty_access = ty.unwrap();
assert!(is_valid_atomic_transaction_ty(ty_access));
let rm = RegMem::mem(addr);
if ty_access == types::I64 {
ctx.emit(Inst::mov64_rm_r(rm, data));
} else {
let ext_mode = ExtMode::new(ty_access.bits(), 64).unwrap_or_else(|| {
panic!(
"invalid extension during AtomicLoad: {} -> {}",
ty_access.bits(),
64
)
});
ctx.emit(Inst::movzx_rm_r(ext_mode, rm, data));
}
implemented_in_isle(ctx);
}
Opcode::AtomicStore => {
// This is a normal store, followed by an `mfence` instruction.
let data = put_input_in_reg(ctx, inputs[0]);
let addr = lower_to_amode(ctx, inputs[1], 0);
let ty_access = ctx.input_ty(insn, 0);
assert!(is_valid_atomic_transaction_ty(ty_access));
ctx.emit(Inst::store(ty_access, data, addr));
ctx.emit(Inst::Fence {
kind: FenceKind::MFence,
});
implemented_in_isle(ctx);
}
Opcode::Fence => {
ctx.emit(Inst::Fence {
kind: FenceKind::MFence,
});
implemented_in_isle(ctx);
}
Opcode::FuncAddr => {