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x64: port some atomics to ISLE (#4212)

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* x64: port `fence` to ISLE
* x64: port `atomic_load` to ISLE
* x64: port `atomic_store` to ISLE
This commit is contained in:
Andrew Brown
2022-06-02 14:13:10 -07:00
committed by GitHub
parent 44d1dee76e
commit 816aae6aca
7 changed files with 58 additions and 43 deletions
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31
cranelift/codegen/src/isa/x64/lower.isle
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@@ -2781,3 +2781,34 @@
(let ((_ RegMemImm (sink_load sink)))
(side_effect
(x64_xor_mem ty (to_amode flags addr offset) src2))))
;; Rules for `fence` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (fence))
(side_effect (x64_mfence)))
;; Rules for `atomic_load` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; This is a normal load. The x86-TSO memory model provides sufficient
;; sequencing to satisfy the CLIF synchronisation requirements for `AtomicLoad`
;; without the need for any fence instructions.
;;
;; As described in the `atomic_load` documentation, this lowering is only valid
;; for I8, I16, I32, and I64. The sub-64-bit types are zero extended, as with a
;; normal load.
(rule (lower (has_type $I64 (atomic_load flags address)))
(x64_mov (to_amode flags address (zero_offset))))
(rule (lower (has_type (and (fits_in_32 ty) (ty_int _)) (atomic_load flags address)))
(x64_movzx (ext_mode (ty_bits_u16 ty) 64) (to_amode flags address (zero_offset))))
;; Rules for `atomic_store` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; This is a normal store followed by an `mfence` instruction. As described in
;; the `atomic_load` documentation, this lowering is only valid for I8, I16,
;; I32, and I64.
(rule (lower (atomic_store flags
value @ (value_type (and (fits_in_64 ty) (ty_int _)))
address))
(side_effect (side_effect_concat
(x64_movrm ty (to_amode flags address (zero_offset)) value)
(x64_mfence))))