diff --git a/cranelift/codegen/src/isa/x64/inst/mod.rs b/cranelift/codegen/src/isa/x64/inst/mod.rs index 3ab8f89b12..f40d3c46e3 100644 --- a/cranelift/codegen/src/isa/x64/inst/mod.rs +++ b/cranelift/codegen/src/isa/x64/inst/mod.rs @@ -1301,36 +1301,6 @@ impl Inst { } } - /// Choose which instruction to use for computing a bitwise AND on two values. - pub(crate) fn and(ty: Type, from: RegMem, to: Writable) -> Inst { - match ty { - types::F32X4 => Inst::xmm_rm_r(SseOpcode::Andps, from, to), - types::F64X2 => Inst::xmm_rm_r(SseOpcode::Andpd, from, to), - _ if ty.is_vector() && ty.bits() == 128 => Inst::xmm_rm_r(SseOpcode::Pand, from, to), - _ => unimplemented!("unimplemented type for Inst::and: {}", ty), - } - } - - /// Choose which instruction to use for computing a bitwise AND NOT on two values. - pub(crate) fn and_not(ty: Type, from: RegMem, to: Writable) -> Inst { - match ty { - types::F32X4 => Inst::xmm_rm_r(SseOpcode::Andnps, from, to), - types::F64X2 => Inst::xmm_rm_r(SseOpcode::Andnpd, from, to), - _ if ty.is_vector() && ty.bits() == 128 => Inst::xmm_rm_r(SseOpcode::Pandn, from, to), - _ => unimplemented!("unimplemented type for Inst::and_not: {}", ty), - } - } - - /// Choose which instruction to use for computing a bitwise OR on two values. - pub(crate) fn or(ty: Type, from: RegMem, to: Writable) -> Inst { - match ty { - types::F32X4 => Inst::xmm_rm_r(SseOpcode::Orps, from, to), - types::F64X2 => Inst::xmm_rm_r(SseOpcode::Orpd, from, to), - _ if ty.is_vector() && ty.bits() == 128 => Inst::xmm_rm_r(SseOpcode::Por, from, to), - _ => unimplemented!("unimplemented type for Inst::or: {}", ty), - } - } - /// Translate three-operand instructions into a sequence of two-operand /// instructions. /// diff --git a/cranelift/codegen/src/isa/x64/lower.isle b/cranelift/codegen/src/isa/x64/lower.isle index 06d064f7d7..183753c2dc 100644 --- a/cranelift/codegen/src/isa/x64/lower.isle +++ b/cranelift/codegen/src/isa/x64/lower.isle @@ -360,18 +360,14 @@ ;; SSE. -(rule (lower (has_type $F32X4 (band x y))) - (value_reg (andps (put_in_reg x) - (put_in_reg_mem y)))) +(decl sse_and (Type Reg RegMem) Reg) +(rule (sse_and $F32X4 x y) (andps x y)) +(rule (sse_and $F64X2 x y) (andpd x y)) +(rule (sse_and (multi_lane _bits _lanes) x y) (pand x y)) -(rule (lower (has_type $F64X2 (band x y))) - (value_reg (andpd (put_in_reg x) - (put_in_reg_mem y)))) - -(rule (lower (has_type (multi_lane _bits _lanes) +(rule (lower (has_type ty @ (multi_lane _bits _lanes) (band x y))) - (value_reg (pand (put_in_reg x) - (put_in_reg_mem y)))) + (value_reg (sse_and ty (put_in_reg x) (put_in_reg_mem y)))) ;; `{i,b}128`. @@ -436,18 +432,14 @@ ;; SSE. -(rule (lower (has_type $F32X4 (bor x y))) - (value_reg (orps (put_in_reg x) - (put_in_reg_mem y)))) +(decl sse_or (Type Reg RegMem) Reg) +(rule (sse_or $F32X4 x y) (orps x y)) +(rule (sse_or $F64X2 x y) (orpd x y)) +(rule (sse_or (multi_lane _bits _lanes) x y) (por x y)) -(rule (lower (has_type $F64X2 (bor x y))) - (value_reg (orpd (put_in_reg x) - (put_in_reg_mem y)))) - -(rule (lower (has_type (multi_lane _bits _lanes) +(rule (lower (has_type ty @ (multi_lane _bits _lanes) (bor x y))) - (value_reg (por (put_in_reg x) - (put_in_reg_mem y)))) + (value_reg (sse_or ty (put_in_reg x) (put_in_reg_mem y)))) ;; `{i,b}128`. @@ -960,6 +952,11 @@ ;;;; Rules for `band_not` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +(decl sse_and_not (Type Reg RegMem) Reg) +(rule (sse_and_not $F32X4 x y) (andnps x y)) +(rule (sse_and_not $F64X2 x y) (andnpd x y)) +(rule (sse_and_not (multi_lane _bits _lanes) x y) (pandn x y)) + ;; Note the flipping of operands below. CLIF specifies ;; ;; band_not(x, y) = and(x, not(y)) @@ -967,15 +964,10 @@ ;; while x86 does ;; ;; pandn(x, y) = and(not(x), y) - -(rule (lower (has_type $F32X4 (band_not x y))) - (value_reg (andnps (put_in_reg y) (put_in_reg_mem x)))) - -(rule (lower (has_type $F64X2 (band_not x y))) - (value_reg (andnpd (put_in_reg y) (put_in_reg_mem x)))) - -(rule (lower (has_type (multi_lane _bits _lanes) (band_not x y))) - (value_reg (pandn (put_in_reg y) (put_in_reg_mem x)))) +(rule (lower (has_type ty (band_not x y))) + (value_reg (sse_and_not ty + (put_in_reg y) + (put_in_reg_mem x)))) ;;;; Rules for `iabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -1044,6 +1036,20 @@ (rule (lower (has_type ty @ (multi_lane _bits _lanes) (bnot x))) (value_reg (sse_xor ty (put_in_reg x) (RegMem.Reg (vector_all_ones ty))))) +;;;; Rules for `bitselect` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(rule (lower (has_type ty @ (multi_lane _bits _lanes) + (bitselect condition + if_true + if_false))) + ;; a = and if_true, condition + ;; b = and_not condition, if_false + ;; or b, a + (let ((cond_reg Reg (put_in_reg condition)) + (a Reg (sse_and ty (put_in_reg if_true) (RegMem.Reg cond_reg))) + (b Reg (sse_and_not ty cond_reg (put_in_reg_mem if_false)))) + (value_reg (sse_or ty b (RegMem.Reg a))))) + ;;;; Rules for `insertlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (rule (lower (insertlane vec @ (value_type ty) val (u8_from_uimm8 idx))) diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs index d0d0debfdf..4093fef0e8 100644 --- a/cranelift/codegen/src/isa/x64/lower.rs +++ b/cranelift/codegen/src/isa/x64/lower.rs @@ -1534,30 +1534,8 @@ fn lower_insn_to_regs>( | Opcode::Umax | Opcode::Imin | Opcode::Umin - | Opcode::Bnot => implemented_in_isle(ctx), - - Opcode::Bitselect => { - let ty = ty.unwrap(); - let condition = put_input_in_reg(ctx, inputs[0]); - let if_true = put_input_in_reg(ctx, inputs[1]); - let if_false = input_to_reg_mem(ctx, inputs[2]); - let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap(); - - if ty.is_vector() { - let tmp1 = ctx.alloc_tmp(ty).only_reg().unwrap(); - ctx.emit(Inst::gen_move(tmp1, if_true, ty)); - ctx.emit(Inst::and(ty, RegMem::reg(condition.clone()), tmp1)); - - let tmp2 = ctx.alloc_tmp(ty).only_reg().unwrap(); - ctx.emit(Inst::gen_move(tmp2, condition, ty)); - ctx.emit(Inst::and_not(ty, if_false, tmp2)); - - ctx.emit(Inst::gen_move(dst, tmp2.to_reg(), ty)); - ctx.emit(Inst::or(ty, RegMem::from(tmp1), dst)); - } else { - unimplemented!("no lowering for scalar bitselect instruction") - } - } + | Opcode::Bnot + | Opcode::Bitselect => implemented_in_isle(ctx), Opcode::Vselect => { let ty = ty.unwrap(); diff --git a/cranelift/codegen/src/isa/x64/lower/isle/generated_code.manifest b/cranelift/codegen/src/isa/x64/lower/isle/generated_code.manifest index ed5f6a1c0b..d42f252c8a 100644 --- a/cranelift/codegen/src/isa/x64/lower/isle/generated_code.manifest +++ b/cranelift/codegen/src/isa/x64/lower/isle/generated_code.manifest @@ -1,4 +1,4 @@ src/clif.isle f176ef3bba99365 src/prelude.isle babc931e5dc5b4cf src/isa/x64/inst.isle fb5d3ac8e68c46d2 -src/isa/x64/lower.isle d39e01add89178d5 +src/isa/x64/lower.isle 5d66b88a371d4d70 diff --git a/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs index bbfa55047f..c8da4c56bb 100644 --- a/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/x64/lower/isle/generated_code.rs @@ -2109,7 +2109,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 388. + // Rule at src/isa/x64/lower.isle line 384. let expr0_0 = C::put_in_regs(ctx, pattern7_0); let expr1_0: usize = 0; let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); @@ -2178,7 +2178,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 466. + // Rule at src/isa/x64/lower.isle line 458. let expr0_0 = C::put_in_regs(ctx, pattern7_0); let expr1_0: usize = 0; let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); @@ -2194,7 +2194,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 532. + // Rule at src/isa/x64/lower.isle line 524. let expr0_0 = C::put_in_regs(ctx, pattern7_0); let expr1_0: usize = 0; let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); @@ -2215,7 +2215,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Bnot = &pattern5_0 { - // Rule at src/isa/x64/lower.isle line 1039. + // Rule at src/isa/x64/lower.isle line 1031. let expr0_0 = constructor_i128_not(ctx, pattern5_1)?; return Some(expr0_0); } @@ -2298,7 +2298,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 727. + // Rule at src/isa/x64/lower.isle line 719. let expr0_0 = C::put_in_regs(ctx, pattern7_0); let expr1_0: usize = 0; let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); @@ -2334,7 +2334,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 378. + // Rule at src/isa/x64/lower.isle line 374. let expr0_0 = C::put_in_regs(ctx, pattern7_0); let expr1_0: usize = 0; let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); @@ -2357,7 +2357,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 463. + // Rule at src/isa/x64/lower.isle line 455. let expr0_0 = C::put_in_regs(ctx, pattern7_0); let expr1_0 = C::put_in_regs(ctx, pattern7_1); let expr2_0 = constructor_or_i128(ctx, expr0_0, expr1_0)?; @@ -2366,7 +2366,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 522. + // Rule at src/isa/x64/lower.isle line 514. let expr0_0 = C::put_in_regs(ctx, pattern7_0); let expr1_0: usize = 0; let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); @@ -2389,7 +2389,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 660. + // Rule at src/isa/x64/lower.isle line 652. let expr0_0 = C::put_in_regs(ctx, pattern7_0); let expr1_0 = constructor_lo_reg(ctx, pattern7_1)?; let expr2_0 = constructor_shl_i128(ctx, expr0_0, expr1_0)?; @@ -2406,7 +2406,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 582. + // Rule at src/isa/x64/lower.isle line 574. let expr0_0 = constructor_lo_reg(ctx, pattern7_1)?; let expr1_0 = C::put_in_regs(ctx, pattern7_0); let expr2_0 = constructor_shl_i128(ctx, expr1_0, expr0_0)?; @@ -2415,7 +2415,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 628. + // Rule at src/isa/x64/lower.isle line 620. let expr0_0 = constructor_lo_reg(ctx, pattern7_1)?; let expr1_0 = C::put_in_regs(ctx, pattern7_0); let expr2_0 = constructor_shr_i128(ctx, expr1_0, expr0_0)?; @@ -2429,7 +2429,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Bnot = &pattern5_0 { - // Rule at src/isa/x64/lower.isle line 1036. + // Rule at src/isa/x64/lower.isle line 1028. let expr0_0 = constructor_i128_not(ctx, pattern5_1)?; return Some(expr0_0); } @@ -2474,7 +2474,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 1117. + // Rule at src/isa/x64/lower.isle line 1123. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); let expr2_0 = constructor_pminsb(ctx, expr0_0, &expr1_0)?; @@ -2484,7 +2484,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 1139. + // Rule at src/isa/x64/lower.isle line 1145. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); let expr2_0 = constructor_pminub(ctx, expr0_0, &expr1_0)?; @@ -2494,7 +2494,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 1106. + // Rule at src/isa/x64/lower.isle line 1112. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); let expr2_0 = constructor_pmaxsb(ctx, expr0_0, &expr1_0)?; @@ -2504,7 +2504,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 1128. + // Rule at src/isa/x64/lower.isle line 1134. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); let expr2_0 = constructor_pmaxub(ctx, expr0_0, &expr1_0)?; @@ -2519,7 +2519,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Iabs = &pattern5_0 { - // Rule at src/isa/x64/lower.isle line 982. + // Rule at src/isa/x64/lower.isle line 974. let expr0_0 = C::put_in_reg_mem(ctx, pattern5_1); let expr1_0 = constructor_pabsb(ctx, &expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); @@ -2540,7 +2540,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 1120. + // Rule at src/isa/x64/lower.isle line 1126. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); let expr2_0 = constructor_pminsw(ctx, expr0_0, &expr1_0)?; @@ -2550,7 +2550,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 1142. + // Rule at src/isa/x64/lower.isle line 1148. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); let expr2_0 = constructor_pminuw(ctx, expr0_0, &expr1_0)?; @@ -2560,7 +2560,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 1109. + // Rule at src/isa/x64/lower.isle line 1115. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); let expr2_0 = constructor_pmaxsw(ctx, expr0_0, &expr1_0)?; @@ -2570,7 +2570,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 1131. + // Rule at src/isa/x64/lower.isle line 1137. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); let expr2_0 = constructor_pmaxuw(ctx, expr0_0, &expr1_0)?; @@ -2585,7 +2585,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Iabs = &pattern5_0 { - // Rule at src/isa/x64/lower.isle line 985. + // Rule at src/isa/x64/lower.isle line 977. let expr0_0 = C::put_in_reg_mem(ctx, pattern5_1); let expr1_0 = constructor_pabsw(ctx, &expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); @@ -2606,7 +2606,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 1123. + // Rule at src/isa/x64/lower.isle line 1129. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); let expr2_0 = constructor_pminsd(ctx, expr0_0, &expr1_0)?; @@ -2616,7 +2616,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 1145. + // Rule at src/isa/x64/lower.isle line 1151. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); let expr2_0 = constructor_pminud(ctx, expr0_0, &expr1_0)?; @@ -2626,7 +2626,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 1112. + // Rule at src/isa/x64/lower.isle line 1118. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); let expr2_0 = constructor_pmaxsd(ctx, expr0_0, &expr1_0)?; @@ -2636,7 +2636,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 1134. + // Rule at src/isa/x64/lower.isle line 1140. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); let expr2_0 = constructor_pmaxud(ctx, expr0_0, &expr1_0)?; @@ -2651,7 +2651,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Iabs = &pattern5_0 { - // Rule at src/isa/x64/lower.isle line 988. + // Rule at src/isa/x64/lower.isle line 980. let expr0_0 = C::put_in_reg_mem(ctx, pattern5_1); let expr1_0 = constructor_pabsd(ctx, &expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); @@ -2669,7 +2669,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { - match &pattern5_0 { - &Opcode::Band => { - let (pattern7_0, pattern7_1) = - C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 363. - let expr0_0 = C::put_in_reg(ctx, pattern7_0); - let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); - let expr2_0 = constructor_andps(ctx, expr0_0, &expr1_0)?; - let expr3_0 = C::value_reg(ctx, expr2_0); - return Some(expr3_0); - } - &Opcode::Bor => { - let (pattern7_0, pattern7_1) = - C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 439. - let expr0_0 = C::put_in_reg(ctx, pattern7_0); - let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); - let expr2_0 = constructor_orps(ctx, expr0_0, &expr1_0)?; - let expr3_0 = C::value_reg(ctx, expr2_0); - return Some(expr3_0); - } - &Opcode::BandNot => { - let (pattern7_0, pattern7_1) = - C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 971. - let expr0_0 = C::put_in_reg(ctx, pattern7_1); - let expr1_0 = C::put_in_reg_mem(ctx, pattern7_0); - let expr2_0 = constructor_andnps(ctx, expr0_0, &expr1_0)?; - let expr3_0 = C::value_reg(ctx, expr2_0); - return Some(expr3_0); - } - _ => {} - } + if let &InstructionData::Unary { + opcode: ref pattern5_0, + arg: pattern5_1, + } = &pattern4_0 + { + if let &Opcode::Fabs = &pattern5_0 { + // Rule at src/isa/x64/lower.isle line 1002. + let expr0_0 = C::put_in_reg(ctx, pattern5_1); + let expr1_0: Type = F32X4; + let expr2_0 = constructor_vector_all_ones(ctx, expr1_0)?; + let expr3_0: u32 = 1; + let expr4_0 = RegMemImm::Imm { simm32: expr3_0 }; + let expr5_0 = constructor_psrld(ctx, expr2_0, &expr4_0)?; + let expr6_0 = RegMem::Reg { reg: expr5_0 }; + let expr7_0 = constructor_andps(ctx, expr0_0, &expr6_0)?; + let expr8_0 = C::value_reg(ctx, expr7_0); + return Some(expr8_0); } - &InstructionData::Unary { - opcode: ref pattern5_0, - arg: pattern5_1, - } => { - if let &Opcode::Fabs = &pattern5_0 { - // Rule at src/isa/x64/lower.isle line 1010. - let expr0_0 = C::put_in_reg(ctx, pattern5_1); - let expr1_0: Type = F32X4; - let expr2_0 = constructor_vector_all_ones(ctx, expr1_0)?; - let expr3_0: u32 = 1; - let expr4_0 = RegMemImm::Imm { simm32: expr3_0 }; - let expr5_0 = constructor_psrld(ctx, expr2_0, &expr4_0)?; - let expr6_0 = RegMem::Reg { reg: expr5_0 }; - let expr7_0 = constructor_andps(ctx, expr0_0, &expr6_0)?; - let expr8_0 = C::value_reg(ctx, expr7_0); - return Some(expr8_0); - } - } - _ => {} } } if pattern2_0 == F64X2 { let pattern4_0 = C::inst_data(ctx, pattern0_0); - match &pattern4_0 { - &InstructionData::Binary { - opcode: ref pattern5_0, - args: ref pattern5_1, - } => { - match &pattern5_0 { - &Opcode::Band => { - let (pattern7_0, pattern7_1) = - C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 367. - let expr0_0 = C::put_in_reg(ctx, pattern7_0); - let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); - let expr2_0 = constructor_andpd(ctx, expr0_0, &expr1_0)?; - let expr3_0 = C::value_reg(ctx, expr2_0); - return Some(expr3_0); - } - &Opcode::Bor => { - let (pattern7_0, pattern7_1) = - C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 443. - let expr0_0 = C::put_in_reg(ctx, pattern7_0); - let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); - let expr2_0 = constructor_orpd(ctx, expr0_0, &expr1_0)?; - let expr3_0 = C::value_reg(ctx, expr2_0); - return Some(expr3_0); - } - &Opcode::BandNot => { - let (pattern7_0, pattern7_1) = - C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 974. - let expr0_0 = C::put_in_reg(ctx, pattern7_1); - let expr1_0 = C::put_in_reg_mem(ctx, pattern7_0); - let expr2_0 = constructor_andnpd(ctx, expr0_0, &expr1_0)?; - let expr3_0 = C::value_reg(ctx, expr2_0); - return Some(expr3_0); - } - _ => {} - } + if let &InstructionData::Unary { + opcode: ref pattern5_0, + arg: pattern5_1, + } = &pattern4_0 + { + if let &Opcode::Fabs = &pattern5_0 { + // Rule at src/isa/x64/lower.isle line 1007. + let expr0_0 = C::put_in_reg(ctx, pattern5_1); + let expr1_0: Type = F64X2; + let expr2_0 = constructor_vector_all_ones(ctx, expr1_0)?; + let expr3_0: u32 = 1; + let expr4_0 = RegMemImm::Imm { simm32: expr3_0 }; + let expr5_0 = constructor_psrlq(ctx, expr2_0, &expr4_0)?; + let expr6_0 = RegMem::Reg { reg: expr5_0 }; + let expr7_0 = constructor_andpd(ctx, expr0_0, &expr6_0)?; + let expr8_0 = C::value_reg(ctx, expr7_0); + return Some(expr8_0); } - &InstructionData::Unary { - opcode: ref pattern5_0, - arg: pattern5_1, - } => { - if let &Opcode::Fabs = &pattern5_0 { - // Rule at src/isa/x64/lower.isle line 1015. - let expr0_0 = C::put_in_reg(ctx, pattern5_1); - let expr1_0: Type = F64X2; - let expr2_0 = constructor_vector_all_ones(ctx, expr1_0)?; - let expr3_0: u32 = 1; - let expr4_0 = RegMemImm::Imm { simm32: expr3_0 }; - let expr5_0 = constructor_psrlq(ctx, expr2_0, &expr4_0)?; - let expr6_0 = RegMem::Reg { reg: expr5_0 }; - let expr7_0 = constructor_andpd(ctx, expr0_0, &expr6_0)?; - let expr8_0 = C::value_reg(ctx, expr7_0); - return Some(expr8_0); - } - } - _ => {} } } let pattern3_0 = C::inst_data(ctx, pattern0_0); - if let &InstructionData::NullAry { - opcode: ref pattern4_0, - } = &pattern3_0 - { - if let &Opcode::Null = &pattern4_0 { - // Rule at src/isa/x64/lower.isle line 56. - let expr0_0: u64 = 0; - let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?; - let expr2_0 = C::value_reg(ctx, expr1_0); - return Some(expr2_0); + match &pattern3_0 { + &InstructionData::NullAry { + opcode: ref pattern4_0, + } => { + if let &Opcode::Null = &pattern4_0 { + // Rule at src/isa/x64/lower.isle line 56. + let expr0_0: u64 = 0; + let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?; + let expr2_0 = C::value_reg(ctx, expr1_0); + return Some(expr2_0); + } } + &InstructionData::Binary { + opcode: ref pattern4_0, + args: ref pattern4_1, + } => { + if let &Opcode::BandNot = &pattern4_0 { + let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, &pattern4_1); + // Rule at src/isa/x64/lower.isle line 967. + let expr0_0 = C::put_in_reg(ctx, pattern6_1); + let expr1_0 = C::put_in_reg_mem(ctx, pattern6_0); + let expr2_0 = constructor_sse_and_not(ctx, pattern2_0, expr0_0, &expr1_0)?; + let expr3_0 = C::value_reg(ctx, expr2_0); + return Some(expr3_0); + } + } + _ => {} } if let Some(()) = C::avx512vl_enabled(ctx, pattern2_0) { if let Some(()) = C::avx512dq_enabled(ctx, pattern2_0) { @@ -2834,7 +2770,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { let (pattern9_0, pattern9_1) = C::unpack_value_array_2(ctx, &pattern7_1); - // Rule at src/isa/x64/lower.isle line 670. + // Rule at src/isa/x64/lower.isle line 662. let expr0_0 = C::put_in_reg(ctx, pattern9_0); let expr1_0 = C::put_in_reg_mem(ctx, pattern9_1); let expr2_0 = constructor_pavgb(ctx, expr0_0, &expr1_0)?; @@ -2962,7 +2898,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { let (pattern9_0, pattern9_1) = C::unpack_value_array_2(ctx, &pattern7_1); - // Rule at src/isa/x64/lower.isle line 674. + // Rule at src/isa/x64/lower.isle line 666. let expr0_0 = C::put_in_reg(ctx, pattern9_0); let expr1_0 = C::put_in_reg_mem(ctx, pattern9_1); let expr2_0 = constructor_pavgw(ctx, expr0_0, &expr1_0)?; @@ -3075,7 +3011,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 371. + // Rule at src/isa/x64/lower.isle line 368. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); - let expr2_0 = constructor_pand(ctx, expr0_0, &expr1_0)?; + let expr2_0 = constructor_sse_and(ctx, pattern2_0, expr0_0, &expr1_0)?; let expr3_0 = C::value_reg(ctx, expr2_0); return Some(expr3_0); } &Opcode::Bor => { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 447. + // Rule at src/isa/x64/lower.isle line 440. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); - let expr2_0 = constructor_por(ctx, expr0_0, &expr1_0)?; + let expr2_0 = constructor_sse_or(ctx, pattern2_0, expr0_0, &expr1_0)?; let expr3_0 = C::value_reg(ctx, expr2_0); return Some(expr3_0); } &Opcode::Bxor => { let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 517. + // Rule at src/isa/x64/lower.isle line 509. let expr0_0 = C::put_in_reg(ctx, pattern7_0); let expr1_0 = C::put_in_reg_mem(ctx, pattern7_1); let expr2_0 = constructor_sse_xor(ctx, pattern2_0, expr0_0, &expr1_0)?; let expr3_0 = C::value_reg(ctx, expr2_0); return Some(expr3_0); } - &Opcode::BandNot => { - let (pattern7_0, pattern7_1) = - C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/x64/lower.isle line 977. - let expr0_0 = C::put_in_reg(ctx, pattern7_1); - let expr1_0 = C::put_in_reg_mem(ctx, pattern7_0); - let expr2_0 = constructor_pandn(ctx, expr0_0, &expr1_0)?; - let expr3_0 = C::value_reg(ctx, expr2_0); - return Some(expr3_0); - } _ => {} } } + &InstructionData::Ternary { + opcode: ref pattern5_0, + args: ref pattern5_1, + } => { + if let &Opcode::Bitselect = &pattern5_0 { + let (pattern7_0, pattern7_1, pattern7_2) = + C::unpack_value_array_3(ctx, &pattern5_1); + // Rule at src/isa/x64/lower.isle line 1041. + let expr0_0 = C::put_in_reg(ctx, pattern7_0); + let expr1_0 = C::put_in_reg(ctx, pattern7_1); + let expr2_0 = RegMem::Reg { reg: expr0_0 }; + let expr3_0 = constructor_sse_and(ctx, pattern2_0, expr1_0, &expr2_0)?; + let expr4_0 = C::put_in_reg_mem(ctx, pattern7_2); + let expr5_0 = constructor_sse_and_not(ctx, pattern2_0, expr0_0, &expr4_0)?; + let expr6_0 = RegMem::Reg { reg: expr3_0 }; + let expr7_0 = constructor_sse_or(ctx, pattern2_0, expr5_0, &expr6_0)?; + let expr8_0 = C::value_reg(ctx, expr7_0); + return Some(expr8_0); + } + } &InstructionData::Unary { opcode: ref pattern5_0, arg: pattern5_1, } => { if let &Opcode::Bnot = &pattern5_0 { - // Rule at src/isa/x64/lower.isle line 1044. + // Rule at src/isa/x64/lower.isle line 1036. let expr0_0 = C::put_in_reg(ctx, pattern5_1); let expr1_0 = constructor_vector_all_ones(ctx, pattern2_0)?; let expr2_0 = RegMem::Reg { reg: expr1_0 }; @@ -4140,7 +4086,7 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option { if let &Opcode::Bnot = &pattern5_0 { - // Rule at src/isa/x64/lower.isle line 1023. + // Rule at src/isa/x64/lower.isle line 1015. let expr0_0 = C::put_in_reg(ctx, pattern5_1); let expr1_0 = constructor_not(ctx, pattern3_0, expr0_0)?; let expr2_0 = C::value_reg(ctx, expr1_0); @@ -4455,13 +4401,13 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option( + ctx: &mut C, + arg0: Type, + arg1: Reg, + arg2: &RegMem, +) -> Option { + let pattern0_0 = arg0; + if pattern0_0 == F32X4 { + let pattern2_0 = arg1; + let pattern3_0 = arg2; + // Rule at src/isa/x64/lower.isle line 364. + let expr0_0 = constructor_andps(ctx, pattern2_0, pattern3_0)?; + return Some(expr0_0); + } + if pattern0_0 == F64X2 { + let pattern2_0 = arg1; + let pattern3_0 = arg2; + // Rule at src/isa/x64/lower.isle line 365. + let expr0_0 = constructor_andpd(ctx, pattern2_0, pattern3_0)?; + return Some(expr0_0); + } + if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) { + let pattern2_0 = arg1; + let pattern3_0 = arg2; + // Rule at src/isa/x64/lower.isle line 366. + let expr0_0 = constructor_pand(ctx, pattern2_0, pattern3_0)?; + return Some(expr0_0); + } + return None; +} + +// Generated as internal constructor for term sse_or. +pub fn constructor_sse_or( + ctx: &mut C, + arg0: Type, + arg1: Reg, + arg2: &RegMem, +) -> Option { + let pattern0_0 = arg0; + if pattern0_0 == F32X4 { + let pattern2_0 = arg1; + let pattern3_0 = arg2; + // Rule at src/isa/x64/lower.isle line 436. + let expr0_0 = constructor_orps(ctx, pattern2_0, pattern3_0)?; + return Some(expr0_0); + } + if pattern0_0 == F64X2 { + let pattern2_0 = arg1; + let pattern3_0 = arg2; + // Rule at src/isa/x64/lower.isle line 437. + let expr0_0 = constructor_orpd(ctx, pattern2_0, pattern3_0)?; + return Some(expr0_0); + } + if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) { + let pattern2_0 = arg1; + let pattern3_0 = arg2; + // Rule at src/isa/x64/lower.isle line 438. + let expr0_0 = constructor_por(ctx, pattern2_0, pattern3_0)?; + return Some(expr0_0); + } + return None; +} + // Generated as internal constructor for term or_i128. pub fn constructor_or_i128( ctx: &mut C, @@ -4513,7 +4523,7 @@ pub fn constructor_or_i128( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/x64/lower.isle line 455. + // Rule at src/isa/x64/lower.isle line 447. let expr0_0: usize = 0; let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0); let expr2_0: usize = 1; @@ -4540,7 +4550,7 @@ pub fn constructor_shl_i128( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/x64/lower.isle line 559. + // Rule at src/isa/x64/lower.isle line 551. let expr0_0: usize = 0; let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0); let expr2_0: usize = 1; @@ -4599,7 +4609,7 @@ pub fn constructor_shr_i128( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/x64/lower.isle line 606. + // Rule at src/isa/x64/lower.isle line 598. let expr0_0: usize = 0; let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0); let expr2_0: usize = 1; @@ -4653,10 +4663,42 @@ pub fn constructor_shr_i128( return Some(expr49_0); } +// Generated as internal constructor for term sse_and_not. +pub fn constructor_sse_and_not( + ctx: &mut C, + arg0: Type, + arg1: Reg, + arg2: &RegMem, +) -> Option { + let pattern0_0 = arg0; + if pattern0_0 == F32X4 { + let pattern2_0 = arg1; + let pattern3_0 = arg2; + // Rule at src/isa/x64/lower.isle line 956. + let expr0_0 = constructor_andnps(ctx, pattern2_0, pattern3_0)?; + return Some(expr0_0); + } + if pattern0_0 == F64X2 { + let pattern2_0 = arg1; + let pattern3_0 = arg2; + // Rule at src/isa/x64/lower.isle line 957. + let expr0_0 = constructor_andnpd(ctx, pattern2_0, pattern3_0)?; + return Some(expr0_0); + } + if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) { + let pattern2_0 = arg1; + let pattern3_0 = arg2; + // Rule at src/isa/x64/lower.isle line 958. + let expr0_0 = constructor_pandn(ctx, pattern2_0, pattern3_0)?; + return Some(expr0_0); + } + return None; +} + // Generated as internal constructor for term i128_not. pub fn constructor_i128_not(ctx: &mut C, arg0: Value) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/x64/lower.isle line 1029. + // Rule at src/isa/x64/lower.isle line 1021. let expr0_0 = C::put_in_regs(ctx, pattern0_0); let expr1_0: usize = 0; let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); @@ -4683,7 +4725,7 @@ pub fn constructor_vec_insert_lane( let pattern2_0 = arg1; let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/x64/lower.isle line 1060. + // Rule at src/isa/x64/lower.isle line 1066. let expr0_0 = constructor_pinsrb(ctx, pattern2_0, pattern3_0, pattern4_0)?; return Some(expr0_0); } @@ -4691,7 +4733,7 @@ pub fn constructor_vec_insert_lane( let pattern2_0 = arg1; let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/x64/lower.isle line 1063. + // Rule at src/isa/x64/lower.isle line 1069. let expr0_0 = constructor_pinsrw(ctx, pattern2_0, pattern3_0, pattern4_0)?; return Some(expr0_0); } @@ -4699,7 +4741,7 @@ pub fn constructor_vec_insert_lane( let pattern2_0 = arg1; let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/x64/lower.isle line 1066. + // Rule at src/isa/x64/lower.isle line 1072. let expr0_0 = OperandSize::Size32; let expr1_0 = constructor_pinsrd(ctx, pattern2_0, pattern3_0, pattern4_0, &expr0_0)?; return Some(expr1_0); @@ -4708,7 +4750,7 @@ pub fn constructor_vec_insert_lane( let pattern2_0 = arg1; let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/x64/lower.isle line 1069. + // Rule at src/isa/x64/lower.isle line 1075. let expr0_0 = OperandSize::Size64; let expr1_0 = constructor_pinsrd(ctx, pattern2_0, pattern3_0, pattern4_0, &expr0_0)?; return Some(expr1_0); @@ -4717,7 +4759,7 @@ pub fn constructor_vec_insert_lane( let pattern2_0 = arg1; let pattern3_0 = arg2; let pattern4_0 = arg3; - // Rule at src/isa/x64/lower.isle line 1072. + // Rule at src/isa/x64/lower.isle line 1078. let expr0_0 = C::sse_insertps_lane_imm(ctx, pattern4_0); let expr1_0 = constructor_insertps(ctx, pattern2_0, pattern3_0, expr0_0)?; return Some(expr1_0); @@ -4728,7 +4770,7 @@ pub fn constructor_vec_insert_lane( if let &RegMem::Reg { reg: pattern4_0 } = pattern3_0 { let pattern5_0 = arg3; if pattern5_0 == 0 { - // Rule at src/isa/x64/lower.isle line 1093. + // Rule at src/isa/x64/lower.isle line 1099. let expr0_0 = RegMem::Reg { reg: pattern4_0 }; let expr1_0 = constructor_movsd(ctx, pattern2_0, &expr0_0)?; return Some(expr1_0); @@ -4736,7 +4778,7 @@ pub fn constructor_vec_insert_lane( } let pattern4_0 = arg3; if pattern4_0 == 0 { - // Rule at src/isa/x64/lower.isle line 1094. + // Rule at src/isa/x64/lower.isle line 1100. let expr0_0 = SseOpcode::Movsd; let expr1_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, pattern3_0)?; let expr2_0 = RegMem::Reg { reg: expr1_0 }; @@ -4744,7 +4786,7 @@ pub fn constructor_vec_insert_lane( return Some(expr3_0); } if pattern4_0 == 1 { - // Rule at src/isa/x64/lower.isle line 1102. + // Rule at src/isa/x64/lower.isle line 1108. let expr0_0 = constructor_movlhps(ctx, pattern2_0, pattern3_0)?; return Some(expr0_0); } diff --git a/cranelift/filetests/filetests/isa/x64/simd-bitwise-compile.clif b/cranelift/filetests/filetests/isa/x64/simd-bitwise-compile.clif index b7251f9fe1..607810b2de 100644 --- a/cranelift/filetests/filetests/isa/x64/simd-bitwise-compile.clif +++ b/cranelift/filetests/filetests/isa/x64/simd-bitwise-compile.clif @@ -2,6 +2,87 @@ test compile set enable_simd target x86_64 skylake +function %band_f32x4(f32x4, f32x4) -> f32x4 { +block0(v0: f32x4, v1: f32x4): + v2 = band v0, v1 + return v2 +} +; check: andps +; not: andpd +; not: pand + +function %band_f64x2(f64x2, f64x2) -> f64x2 { +block0(v0: f64x2, v1: f64x2): + v2 = band v0, v1 + return v2 +} +; check: andpd +; not: andps +; not: pand + +function %band_i32x4(i32x4, i32x4) -> i32x4 { +block0(v0: i32x4, v1: i32x4): + v2 = band v0, v1 + return v2 +} +; check: pand +; not: andps +; not: andpd + +function %bor_f32x4(f32x4, f32x4) -> f32x4 { +block0(v0: f32x4, v1: f32x4): + v2 = bor v0, v1 + return v2 +} +; check: orps +; not: orpd +; not: por + +function %bor_f64x2(f64x2, f64x2) -> f64x2 { +block0(v0: f64x2, v1: f64x2): + v2 = bor v0, v1 + return v2 +} +; check: orpd +; not: orps +; not: por + +function %bor_i32x4(i32x4, i32x4) -> i32x4 { +block0(v0: i32x4, v1: i32x4): + v2 = bor v0, v1 + return v2 +} +; check: por +; not: orps +; not: orpd + +function %bxor_f32x4(f32x4, f32x4) -> f32x4 { +block0(v0: f32x4, v1: f32x4): + v2 = bxor v0, v1 + return v2 +} +; check: xorps +; not: xorpd +; not: pxor + +function %bxor_f64x2(f64x2, f64x2) -> f64x2 { +block0(v0: f64x2, v1: f64x2): + v2 = bxor v0, v1 + return v2 +} +; check: xorpd +; not: xorps +; not: pxor + +function %bxor_i32x4(i32x4, i32x4) -> i32x4 { +block0(v0: i32x4, v1: i32x4): + v2 = bxor v0, v1 + return v2 +} +; check: pxor +; not: xorps +; not: xorpd + function %bitselect_i16x8() -> i16x8 { block0: v0 = vconst.i16x8 [0 0 0 0 0 0 0 0] diff --git a/cranelift/filetests/filetests/runtests/simd-bitselect.clif b/cranelift/filetests/filetests/runtests/simd-bitselect.clif new file mode 100644 index 0000000000..4ff5cd2e31 --- /dev/null +++ b/cranelift/filetests/filetests/runtests/simd-bitselect.clif @@ -0,0 +1,14 @@ +test run +set enable_simd +target aarch64 +target x86_64 + +function %bitselect_i32x4(i32x4, i32x4, i32x4) -> i32x4 { +block0(v0: i32x4, v1: i32x4, v2: i32x4): + v3 = bitselect v0, v1, v2 + return v3 +} +; run: %bitselect_i32x4(0x00000000000000000000000000000000, 0x11111111111111111111111111111111, 0x00000000000000000000000000000000) == 0x00000000000000000000000000000000 +; run: %bitselect_i32x4(0x11111111111111111111111111111111, 0x11111111111111111111111111111111, 0x00000000000000000000000000000000) == 0x11111111111111111111111111111111 +; run: %bitselect_i32x4(0x01010011000011110000000011111111, 0x11111111111111111111111111111111, 0x00000000000000000000000000000000) == 0x01010011000011110000000011111111 +; run: %bitselect_i32x4(0x00000000000000001111111111111111, 0x00000000000000000000000000000000, 0x11111111111111111111111111111111) == 0x11111111111111110000000000000000 diff --git a/crates/wasmtime/src/func.rs b/crates/wasmtime/src/func.rs index c011b52d27..3f4b2ad496 100644 --- a/crates/wasmtime/src/func.rs +++ b/crates/wasmtime/src/func.rs @@ -1459,7 +1459,7 @@ macro_rules! impl_wasm_host_results { fn func_type(params: impl Iterator) -> FuncType { FuncType::new( params, - std::array::IntoIter::new([$($t::valtype(),)*]), + IntoIterator::into_iter([$($t::valtype(),)*]), ) } diff --git a/tests/all/limits.rs b/tests/all/limits.rs index 1515197ff9..f1ee6d7c18 100644 --- a/tests/all/limits.rs +++ b/tests/all/limits.rs @@ -28,7 +28,7 @@ fn test_limits() -> Result<()> { let instance = Instance::new(&mut store, &module, &[])?; // Test instance exports and host objects hitting the limit - for memory in std::array::IntoIter::new([ + for memory in IntoIterator::into_iter([ instance.get_memory(&mut store, "m").unwrap(), Memory::new(&mut store, MemoryType::new(0, None))?, ]) { @@ -46,7 +46,7 @@ fn test_limits() -> Result<()> { } // Test instance exports and host objects hitting the limit - for table in std::array::IntoIter::new([ + for table in IntoIterator::into_iter([ instance.get_table(&mut store, "t").unwrap(), Table::new( &mut store, @@ -137,7 +137,7 @@ async fn test_limits_async() -> Result<()> { let instance = Instance::new_async(&mut store, &module, &[]).await?; // Test instance exports and host objects hitting the limit - for memory in std::array::IntoIter::new([ + for memory in IntoIterator::into_iter([ instance.get_memory(&mut store, "m").unwrap(), Memory::new_async(&mut store, MemoryType::new(0, None)).await?, ]) { @@ -156,7 +156,7 @@ async fn test_limits_async() -> Result<()> { } // Test instance exports and host objects hitting the limit - for table in std::array::IntoIter::new([ + for table in IntoIterator::into_iter([ instance.get_table(&mut store, "t").unwrap(), Table::new_async( &mut store, @@ -201,7 +201,7 @@ fn test_limits_memory_only() -> Result<()> { let instance = Instance::new(&mut store, &module, &[])?; // Test instance exports and host objects hitting the limit - for memory in std::array::IntoIter::new([ + for memory in IntoIterator::into_iter([ instance.get_memory(&mut store, "m").unwrap(), Memory::new(&mut store, MemoryType::new(0, None))?, ]) { @@ -219,7 +219,7 @@ fn test_limits_memory_only() -> Result<()> { } // Test instance exports and host objects *not* hitting the limit - for table in std::array::IntoIter::new([ + for table in IntoIterator::into_iter([ instance.get_table(&mut store, "t").unwrap(), Table::new( &mut store, @@ -282,7 +282,7 @@ fn test_limits_table_only() -> Result<()> { let instance = Instance::new(&mut store, &module, &[])?; // Test instance exports and host objects *not* hitting the limit - for memory in std::array::IntoIter::new([ + for memory in IntoIterator::into_iter([ instance.get_memory(&mut store, "m").unwrap(), Memory::new(&mut store, MemoryType::new(0, None))?, ]) { @@ -293,7 +293,7 @@ fn test_limits_table_only() -> Result<()> { } // Test instance exports and host objects hitting the limit - for table in std::array::IntoIter::new([ + for table in IntoIterator::into_iter([ instance.get_table(&mut store, "t").unwrap(), Table::new( &mut store,