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Add Intel encodings for the fcmp instruction.

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Not all floating point condition codes are directly supported by the
ucimiss/ucomisd instructions. Some inequalities need to be reversed and
eq+ne require two separate tests.
This commit is contained in:
Jakob Stoklund Olesen
2017-09-26 09:54:54 -07:00
parent 79968a2325
commit 7fb6159a85
9 changed files with 342 additions and 10 deletions
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60
cranelift/filetests/isa/intel/binary32-float.cton
View File

@@ -157,6 +157,36 @@ ebb0:
; asm: movd 1032(%esp), %xmm2
[-,%xmm2] v211 = fill v201 ; bin: 66 0f 6e 94 24 00000408
; Comparisons.
;
; Only `supported_floatccs` are tested here. Others are handled by
; legalization paterns.
; asm: ucomiss %xmm2, %xmm5
; asm: setnp %bl
[-,%rbx] v300 = fcmp ord v10, v11 ; bin: 0f 2e ea 0f 9b c3
; asm: ucomiss %xmm5, %xmm2
; asm: setp %bl
[-,%rbx] v301 = fcmp uno v11, v10 ; bin: 0f 2e d5 0f 9a c3
; asm: ucomiss %xmm2, %xmm5
; asm: setne %dl
[-,%rdx] v302 = fcmp one v10, v11 ; bin: 0f 2e ea 0f 95 c2
; asm: ucomiss %xmm5, %xmm2
; asm: sete %dl
[-,%rdx] v303 = fcmp ueq v11, v10 ; bin: 0f 2e d5 0f 94 c2
; asm: ucomiss %xmm2, %xmm5
; asm: seta %bl
[-,%rbx] v304 = fcmp gt v10, v11 ; bin: 0f 2e ea 0f 97 c3
; asm: ucomiss %xmm5, %xmm2
; asm: setae %bl
[-,%rbx] v305 = fcmp ge v11, v10 ; bin: 0f 2e d5 0f 93 c3
; asm: ucomiss %xmm2, %xmm5
; asm: setb %dl
[-,%rdx] v306 = fcmp ult v10, v11 ; bin: 0f 2e ea 0f 92 c2
; asm: ucomiss %xmm5, %xmm2
; asm: setbe %dl
[-,%rdx] v307 = fcmp ule v11, v10 ; bin: 0f 2e d5 0f 96 c2
return
}
@@ -302,5 +332,35 @@ ebb0:
; asm: movq 1032(%esp), %xmm2
[-,%xmm2] v211 = fill v201 ; bin: f3 0f 7e 94 24 00000408
; Comparisons.
;
; Only `supported_floatccs` are tested here. Others are handled by
; legalization paterns.
; asm: ucomisd %xmm2, %xmm5
; asm: setnp %bl
[-,%rbx] v300 = fcmp ord v10, v11 ; bin: 66 0f 2e ea 0f 9b c3
; asm: ucomisd %xmm5, %xmm2
; asm: setp %bl
[-,%rbx] v301 = fcmp uno v11, v10 ; bin: 66 0f 2e d5 0f 9a c3
; asm: ucomisd %xmm2, %xmm5
; asm: setne %dl
[-,%rdx] v302 = fcmp one v10, v11 ; bin: 66 0f 2e ea 0f 95 c2
; asm: ucomisd %xmm5, %xmm2
; asm: sete %dl
[-,%rdx] v303 = fcmp ueq v11, v10 ; bin: 66 0f 2e d5 0f 94 c2
; asm: ucomisd %xmm2, %xmm5
; asm: seta %bl
[-,%rbx] v304 = fcmp gt v10, v11 ; bin: 66 0f 2e ea 0f 97 c3
; asm: ucomisd %xmm5, %xmm2
; asm: setae %bl
[-,%rbx] v305 = fcmp ge v11, v10 ; bin: 66 0f 2e d5 0f 93 c3
; asm: ucomisd %xmm2, %xmm5
; asm: setb %dl
[-,%rdx] v306 = fcmp ult v10, v11 ; bin: 66 0f 2e ea 0f 92 c2
; asm: ucomisd %xmm5, %xmm2
; asm: setbe %dl
[-,%rdx] v307 = fcmp ule v11, v10 ; bin: 66 0f 2e d5 0f 96 c2
return
}

60
cranelift/filetests/isa/intel/binary64-float.cton
View File

@@ -166,6 +166,36 @@ ebb0:
; asm: movd 1032(%rsp), %xmm10
[-,%xmm10] v211 = fill v201 ; bin: 66 44 0f 6e 94 24 00000408
; Comparisons.
;
; Only `supported_floatccs` are tested here. Others are handled by
; legalization paterns.
; asm: ucomiss %xmm10, %xmm5
; asm: setnp %bl
[-,%rbx] v300 = fcmp ord v10, v11 ; bin: 41 0f 2e ea 0f 9b c3
; asm: ucomiss %xmm5, %xmm10
; asm: setp %bl
[-,%rbx] v301 = fcmp uno v11, v10 ; bin: 44 0f 2e d5 0f 9a c3
; asm: ucomiss %xmm10, %xmm5
; asm: setne %dl
[-,%rdx] v302 = fcmp one v10, v11 ; bin: 41 0f 2e ea 0f 95 c2
; asm: ucomiss %xmm5, %xmm10
; asm: sete %dl
[-,%rdx] v303 = fcmp ueq v11, v10 ; bin: 44 0f 2e d5 0f 94 c2
; asm: ucomiss %xmm10, %xmm5
; asm: seta %bl
[-,%rbx] v304 = fcmp gt v10, v11 ; bin: 41 0f 2e ea 0f 97 c3
; asm: ucomiss %xmm5, %xmm10
; asm: setae %bl
[-,%rbx] v305 = fcmp ge v11, v10 ; bin: 44 0f 2e d5 0f 93 c3
; asm: ucomiss %xmm10, %xmm5
; asm: setb %dl
[-,%rdx] v306 = fcmp ult v10, v11 ; bin: 41 0f 2e ea 0f 92 c2
; asm: ucomiss %xmm5, %xmm10
; asm: setbe %dl
[-,%rdx] v307 = fcmp ule v11, v10 ; bin: 44 0f 2e d5 0f 96 c2
return
}
@@ -326,5 +356,35 @@ ebb0:
; asm: movq 1032(%rsp), %xmm10
[-,%xmm10] v211 = fill v201 ; bin: f3 44 0f 7e 94 24 00000408
; Comparisons.
;
; Only `supported_floatccs` are tested here. Others are handled by
; legalization paterns.
; asm: ucomisd %xmm10, %xmm5
; asm: setnp %bl
[-,%rbx] v300 = fcmp ord v10, v11 ; bin: 66 41 0f 2e ea 0f 9b c3
; asm: ucomisd %xmm5, %xmm10
; asm: setp %bl
[-,%rbx] v301 = fcmp uno v11, v10 ; bin: 66 44 0f 2e d5 0f 9a c3
; asm: ucomisd %xmm10, %xmm5
; asm: setne %dl
[-,%rdx] v302 = fcmp one v10, v11 ; bin: 66 41 0f 2e ea 0f 95 c2
; asm: ucomisd %xmm5, %xmm10
; asm: sete %dl
[-,%rdx] v303 = fcmp ueq v11, v10 ; bin: 66 44 0f 2e d5 0f 94 c2
; asm: ucomisd %xmm10, %xmm5
; asm: seta %bl
[-,%rbx] v304 = fcmp gt v10, v11 ; bin: 66 41 0f 2e ea 0f 97 c3
; asm: ucomisd %xmm5, %xmm10
; asm: setae %bl
[-,%rbx] v305 = fcmp ge v11, v10 ; bin: 66 44 0f 2e d5 0f 93 c3
; asm: ucomisd %xmm10, %xmm5
; asm: setb %dl
[-,%rdx] v306 = fcmp ult v10, v11 ; bin: 66 41 0f 2e ea 0f 92 c2
; asm: ucomisd %xmm5, %xmm10
; asm: setbe %dl
[-,%rdx] v307 = fcmp ule v11, v10 ; bin: 66 44 0f 2e d5 0f 96 c2
return
}

50
cranelift/filetests/wasm/f32-compares.cton Normal file
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@@ -0,0 +1,50 @@
; Test code generation for WebAssembly f32 comparison operators.
test compile
set is_64bit=0
isa intel haswell
set is_64bit=1
isa intel haswell
function %f32_eq(f32, f32) -> i32 {
ebb0(v0: f32, v1: f32):
v2 = fcmp eq v0, v1
v3 = bint.i32 v2
return v3
}
function %f32_ne(f32, f32) -> i32 {
ebb0(v0: f32, v1: f32):
v2 = fcmp ne v0, v1
v3 = bint.i32 v2
return v3
}
function %f32_lt(f32, f32) -> i32 {
ebb0(v0: f32, v1: f32):
v2 = fcmp lt v0, v1
v3 = bint.i32 v2
return v3
}
function %f32_gt(f32, f32) -> i32 {
ebb0(v0: f32, v1: f32):
v2 = fcmp gt v0, v1
v3 = bint.i32 v2
return v3
}
function %f32_le(f32, f32) -> i32 {
ebb0(v0: f32, v1: f32):
v2 = fcmp le v0, v1
v3 = bint.i32 v2
return v3
}
function %f32_ge(f32, f32) -> i32 {
ebb0(v0: f32, v1: f32):
v2 = fcmp ge v0, v1
v3 = bint.i32 v2
return v3
}

50
cranelift/filetests/wasm/f64-compares.cton Normal file
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@@ -0,0 +1,50 @@
; Test code generation for WebAssembly f64 comparison operators.
test compile
set is_64bit=0
isa intel haswell
set is_64bit=1
isa intel haswell
function %f64_eq(f64, f64) -> i32 {
ebb0(v0: f64, v1: f64):
v2 = fcmp eq v0, v1
v3 = bint.i32 v2
return v3
}
function %f64_ne(f64, f64) -> i32 {
ebb0(v0: f64, v1: f64):
v2 = fcmp ne v0, v1
v3 = bint.i32 v2
return v3
}
function %f64_lt(f64, f64) -> i32 {
ebb0(v0: f64, v1: f64):
v2 = fcmp lt v0, v1
v3 = bint.i32 v2
return v3
}
function %f64_gt(f64, f64) -> i32 {
ebb0(v0: f64, v1: f64):
v2 = fcmp gt v0, v1
v3 = bint.i32 v2
return v3
}
function %f64_le(f64, f64) -> i32 {
ebb0(v0: f64, v1: f64):
v2 = fcmp le v0, v1
v3 = bint.i32 v2
return v3
}
function %f64_ge(f64, f64) -> i32 {
ebb0(v0: f64, v1: f64):
v2 = fcmp ge v0, v1
v3 = bint.i32 v2
return v3
}