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Add i64x2 integer multiplication using AVX512DQ

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This commit is contained in:
Andrew Brown
2020-02-14 13:24:13 -08:00
parent 7d5075a649
commit 7f7196a655
3 changed files with 33 additions and 0 deletions
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12
cranelift/codegen/meta/src/isa/x86/encodings.rs
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@@ -1612,6 +1612,7 @@ fn define_simd(
let x86_ptest = x86.by_name("x86_ptest");
// Shorthands for recipes.
let rec_evex_reg_vvvv_rm_128 = r.template("evex_reg_vvvv_rm_128");
let rec_f_ib = r.template("f_ib");
let rec_fa = r.template("fa");
let rec_fa_ib = r.template("fa_ib");
@@ -1647,6 +1648,7 @@ fn define_simd(
let use_ssse3_simd = settings.predicate_by_name("use_ssse3_simd");
let use_sse41_simd = settings.predicate_by_name("use_sse41_simd");
let use_sse42_simd = settings.predicate_by_name("use_sse42_simd");
let use_avx512dq_simd = settings.predicate_by_name("use_avx512dq_simd");
// SIMD vector size: eventually multiple vector sizes may be supported but for now only
// SSE-sized vectors are available.
@@ -1927,6 +1929,16 @@ fn define_simd(
e.enc_32_64_maybe_isap(imul, rec_fa.opcodes(opcodes), *isap);
}
// SIMD integer multiplication for I64x2 using a AVX512.
{
let imul = imul.bind(vector(I64, sse_vector_size));
e.enc_32_64_maybe_isap(
imul,
rec_evex_reg_vvvv_rm_128.opcodes(&PMULLQ).w(),
Some(use_avx512dq_simd), // TODO need an OR predicate to join with AVX512VL
);
}
// SIMD integer average with rounding.
for (ty, opcodes) in &[(I8, &PAVGB[..]), (I16, &PAVGW[..])] {
let avgr = avg_round.bind(vector(*ty, sse_vector_size));