diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
index f97cd75ef8..d95a92cf91 100644
--- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs
@@ -794,8 +794,8 @@ pub enum Inst {
     },
 
     /// An atomic read-modify-write operation. These instructions require the
-    /// Large System Extension (LSE) ISA support. The instructions have acquire-release
-    /// semantics.
+    /// Large System Extension (LSE) ISA support (FEAT_LSE). The instructions have
+    /// acquire-release semantics.
     AtomicRMW {
         op: AtomicRMWOp,
         rs: Reg,
@@ -3656,9 +3656,7 @@ impl Inst {
                 let cond = cond.show_rru(mb_rru);
                 format!("ccmp {}, {}, {}, {}", rn, imm, nzcv, cond)
             }
-            &Inst::AtomicRMW {
-                rs, rt, rn, ty, op
-            } => {
+            &Inst::AtomicRMW { rs, rt, rn, ty, op } => {
                 let op = match op {
                     AtomicRMWOp::Add => "ldaddal",
                     AtomicRMWOp::Clr => "ldclral",
diff --git a/cranelift/codegen/src/isa/aarch64/lower_inst.rs b/cranelift/codegen/src/isa/aarch64/lower_inst.rs
index c743f642a4..af549e43a4 100644
--- a/cranelift/codegen/src/isa/aarch64/lower_inst.rs
+++ b/cranelift/codegen/src/isa/aarch64/lower_inst.rs
@@ -1540,7 +1540,7 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
                 AtomicRmwOp::Umax => Some(AtomicRMWOp::Umax),
                 AtomicRmwOp::Smin => Some(AtomicRMWOp::Smin),
                 AtomicRmwOp::Umin => Some(AtomicRMWOp::Umin),
-                _ => None
+                _ => None,
             };
             if isa_flags.use_lse() && lse_op.is_some() {
                 ctx.emit(Inst::AtomicRMW {